- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98023 > ML9620GAZ210 (OKI ELECTRIC INDUSTRY CO LTD) 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | ML9620GAZ210 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 4/79頁 |
| 文件大?。?/td> | 449K |
| 代理商： | ML9620GAZ210 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
ML9620 User’s Manual
Chapter 1
Overview
1 – 4
1.6
Pin Description
Table 1-1 Pin Description
Symbol
Pin
Description
CS
I
Chip select pin.
When at a ‘L’, PALE,
PWR, PRD/SRW, SCLK and SDO pins (microcontroller
interface pins) are valid.
When at a ‘H’, these pins are invalid.
A[7:0]
I
Address bus pins (when using separate buses).
If used with a multiplexed bus or if used in the serial mode, fix these pins at
‘H’ or ‘L’ levels.
AD[7:0] / D[7:0]
I/O
Multiplexed bus: Address/data pins (AD7-0).
Separate buses: Data pins (D7-0).
If used in the serial mode, fix these pins at a ‘L’ level.
It becomes an input port at the reset.
PWR
I
Write input pin if used in the parallel mode.
Data is captured when this pin is at a ‘L’ level.
If used in the serial mode, fix
this pin at a ‘L’ level.
PRD / SRW
I
Parallel mode:
Read signal pin (
PRD).
When at a ‘L’ level, data is output from the data pins.
Serial mode:
Read/write signal pin (SR
W).
When at a ‘H’ level, data is output from the SDO pin.
When at a ‘L’ level, the SDO pin output unknown data, and data is captured
beginning with the second byte of data input from the SDI pin.
PALE
I
Address latch signal pin.
When at a ‘H’ level, addresses are captured.
If used in the parallel mode
and the address latch signal is unnecessary or in the serial mode, fix this pin
at a ‘H’ or ‘L’ level.
SDI
I
Serial data input pin.
Addresses (1st byte) and data (beginning from the 2nd byte) are input to this
pin, LSB first.
If used in the parallel mode, fix this pin at a ‘H’ or ‘L’ level.
SDO
O
Serial data output pin.
When the
CS pin is at a ‘H’ level, this pin is at high impedance. When CS is
at a ‘L’ level, data is output from this pin, LSB first. If used in the parallel
mode, fix this pin at a ‘H’ or ‘L’ level.
It becomes a high impedance at the reset.
SCLK
I
Shift clock input pin for serial data.
At the rising edge of the shift clock, SDI pin data is captured.
At the falling
edge, data is output from the SDO pin. If used in the parallel mode, fix this
pin at a ‘H’ or ‘L’ level.
PRDY / SWAIT
O
Ready output pin.
Requests wait cycles in read/write access to interface registers.
This signal
maintains the request until the internal access bewteen IFm registers and
Message RAM is completed.
Internal access in
progress
After completion of
access
Parallel mode(
PRDY)
‘L’ level output
High impedance output
Serial mode(SWAIT)
‘H’ level output
‘L’ level output
It becomes a high impedance at the reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MLX90308LUD-CAB | MICROCONTROLLER, UUC |
| MM58167MWC | 0 TIMER(S), REAL TIME CLOCK, UUC24 |
| MM58274CVX | 0 TIMER(S), REAL TIME CLOCK, PQCC20 |
| MM908E621ACDWB/R2 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
| MM908E621ACDWB | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML9620GAZ23A-7 | 制造商:ROHM Semiconductor 功能描述: |
| ML9620GAZ23B | 制造商:ROHM Semiconductor 功能描述:CAN BUS CONTROLLER |
| ML9620GAZ23B-7 | 制造商:ROHM Semiconductor 功能描述: |
| ML9649-001CVWA-5017 | 制造商:ROHM Semiconductor 功能描述:RHOML9649-001CVWA-5017 OKI LCD DRIVER |
| ML9649-007CVWA-5017 | 制造商:ROHM Semiconductor 功能描述:RHOML9649-007CVWA-5017 OKI LCD DRIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。