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ML9620 User’s Manual
Chapter 3
Operational Description
3 - 11
3.9
Handling Interrupt
If several interrupts are pending the CAN Interrupt Register will point to the pending interrupt with the highest
priority, disregarding their chronological order.
An interrupt remains pending until the MCU has cleared it.
The Status Interrupt has the highest priority.
Among the message interrupts, the Message Object’ s interrupt
priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s IntPnd bit.
The Status Interrupt is cleared by
reading the Status Register.
The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt.
When no interrupt is
pending the register will hold the value ‘0’.
If the value of the Interrupt Register is different from ‘0’, then there
is an interrupt pending and, if IE is set, the interrupt line to the MCU,
INT, is active. The interrupt line remains
active until the Interrupt Register is back to value ‘0’ (the cause of the interrupt is reset) or until IE is reset.
The value 0x80 indicates that an interrupt is pending because the CAN Control has updated (not necessarily
changed) the Status Register (Error Interrupt or Status Interrupt).
This interrupt has the highest priority.
The
MCU can update (reset) the status bits RxOK, TxOK and LEC, but a write access of the MCU to the Status
Register can never generate or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects, IntId points to the pending
message interrupt with the highest interrupt priority.
The MCU controls whether a change of the Status Register may cause an interrupt (bits EIE and SIE in the CAN
Control Register) and whether the interrupt line becomes active when the Interrupt Register is different from ‘0’
(bit IE in the CAN Control Register).
The Interrupt Register will be updated even when IE is reset.
The MCU has two possibilities to follow the source of a message interrupt.
First it can follow the IntId in the
Interrupt Register and second it can poll the Interrupt Pending Register (see section 2.4.4).
An interrupt service routine reading the message that is the source of the interrupt may read the message and reset
the Message Object’s IntPnd at the same time (bit ClrIntPnd in the Command Mask Register).
When IntPnd is
cleared, the Interrupt Register will point to the next Message Object with a pending interrupt.