參數(shù)資料
型號(hào): ML9620GAZ210
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù): 50/79頁(yè)
文件大?。?/td> 449K
代理商: ML9620GAZ210
ML9620 User’s Manual
Chapter 3
Operational Description
3 - 14
3.10.3 Configuration of the CAN Protocol Controller
In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n], values in the
range of [0..n-1] are programmed.
That way, e.g. SJW (functional range of [1..4]) is represented by only two
bits.
Therefore the length of the bit time is (programmed value) [TSEG1 + TSEG2 + 3] tq or (functional values)
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The data in the bit timing registers are the configuration input of the CAN protocol controller.
The Baud Rate
Prescaler (configured by BRP) defines the length of the time quantum, the basic time unit of the bit time; the Bit
Timing Logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in the bit time.
3.10.4 Calculation of the Bit Timing Parameter
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.
The resulting bit
time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta, the length of the time quantum tq is defined by the Baud Rate
Prescaler with tq = (Baud Rate Prescaler)/fsys. Several combinations may lead to the desired bit time, allowing
iterations of the following steps.
First part of the bit time to be defined is the Prop_Seg.
Its length depends on the delay times measured in the
system. A maximum bus length as well as a maximum node delay has to be defined for expandible CAN bus
systems.
The resulting time for Prop_Seg is converted into time quanta (rounded up to the nearest integer
multiple of tq).
The Sync_Seg is 1 tq long (fixed), leaving (bit time – Prop_Seg – 1) tq for the two Phase Buffer Segments.
If the
number of remaining tq is even, the Phase Buffer Segments have the same length, Phase_Seg2
= Phase_Seg1, else
Phase_Seg2
= Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 has to be regarded as well.
Phase_Seg2 may not be shorter than the
CAN controller’s Information Processing Time, which is, depending on the actual implementation, in the range of
[0..2] tq.
The length of the Synchronisation Jump Width is set to its maximum value, which is the minimum of 4 and
Phase_Seg1.
CAN nodes with different system clocks require different configurations to come to the same bit rate.
The
calculation of the propagation time in the CAN network, based on the nodes with the longest delay times, is done
once for the whole network.
The calculation may show that bus length or bit rate have to be decreased or that the oscilator frequencies’ stability
has to be increased in order to find a protocol compliant configuration of the CAN bit timing.
The resulting configuration is written into the Bit Timing Register :
(Phase_Seg2-1) & (Phase_Seg1 + Prop_Seg - 1) & (SynchronisationJumpWidth - 1) & (Prescaler - 1)
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