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| 型號： | ML9620GAZ210 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 10/79頁 |
| 文件大?。?/td> | 449K |
| 代理商： | ML9620GAZ210 |
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ML9620 User’s Manual
Chapter 2
Register Descriptions
2 – 1
Chapter 2
Register Descriptions
2.1
Hardware Reset Description
After hardware reset, the registers of the ML9620 hold the values described in table 1-2.
Additionally the busoff state is reset and the output TX is set to recessive (HIGH).
The reset value 0x01 (Init =
‘1’) in the CAN Control Register enables the software initialization.
The ML9620 does not affect the CAN bus
until the MCU resets Init to ‘0’.
The data stored in the Message RAM is not affected by a hardware reset.
After power-on, the contents of the
Message RAM are undefined.
2.2
CAN Protocol Related Registers
These registers (chapter 2.2.1 to 2.2.9) control the operating modes and the configuration of the CAN bit timing
and provide status information.
Real address = Base address for ML9620 + Offset address :
Base address for ML9620 : CAN Base
2.2.1 CAN Control register (CANCONT)
7
6
5
4
3
2
1
0
CANCONT
Option
CCE
DAR
-*
EIE
SIE
IE
Init
reset value
0
1
Address
: CAN Base + 0x00
Access
: R/W
Access Size : 8 bits
Note
‘-’ : Reserved bits return '0' for reads and should be written '0' to them.
Operation is not guaranteed for a
writing '1' to them.
Bit Descriptions
Init
Initialization
0
Normal Operation.
1
Initialization is started.
IE
Interrupt Enable
0
Interrupt
INT is always HIGH.
1
Interrupts will set
INT to LOW. INT remains LOW until all pending interrupts are
processed.
SIE
Status Chage Interrupt Enable
0
No Status Interrupt will be detected.
1
An interrupt will be generated when a message transfer is successfully
completed or a CAN bus error is detected. (while IE=‘1’)
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