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參數(shù)資料
| 型號： | ML9620GAZ210 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 49/79頁 |
| 文件大小： | 449K |
| 代理商： | ML9620GAZ210 |
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ML9620 User’s Manual
Chapter 3
Operational Description
3 - 13
A given bit rate may be met by different bit time configurations, but for the proper function of the CAN network
the physical delay times and the oscillator’s tolerance range have to be considered.
3.10.2 Propagation Time Segment
This part of the bit time is used to compensate physical delay times within the network.
These delay times
consist of the signal propagation time on the bus and the internal delay time of the CAN nodes.
Any CAN node synchronised to the bit stream on the CAN bus will be out of phase with the transmitter of that bit
stream, caused by the signal propagation time between the two nodes.
The CAN protocol’s non-destructive
bitwise arbitration and the dominant acknowledge bit provided by receivers of CAN messages require that a CAN
node transmitting a bit stream must also be able to receive dominant bits transmitted by other CAN nodes that are
synchronised to that bit stream.
The example in figure 3-7 shows the phase shift and propagation times between
two CAN nodes.
Sync
Seg.
Prop. Seg.
Phase Seg. 1
Phase Seg. 2
Sync
Seg.
Prop. Seg.
Phase Seg. 1
Phase Seg. 2
Sync
Seg.
Prop. Seg.
Phase Seg. 1
Phase Seg. 2
Sync
Seg.
Prop. Seg.
Phase Seg. 1
Node A
Node B
Delay A to B
Delay B to A
Delay A to B
>= node output delay(A) + bus line delay(A to B) + node input delay(B)
Prop. Seg.
>= Delay A to B + Delay B to A
Prop. Seg.
>= 2 [max(node output delay + bus line delay + node input delay)]
Figure 3-7 Propagation Time Segment
In this example, both nodes A and B are transmitters performing an arbitration for the CAN bus.
The node A has
sent its Start of Frame bit less than one bit time earlier than node B, therefore node B has synchronised itself to the
received edge from recessive to dominant.
Since node B has received this edge delay (A to B) after it has been
transmitted, B’s bit timing segments are shifted with regard to A.
Node B sends an identifier with higher priority
and so it will win the arbitration at a specific identifier bit when it transmits a dominant bit while node A transmits
a recessive bit.
The dominant bit transmitted by node B will arrive at node A after the delay (B to A).
Due to oscillator tolerances, the actual position of node A’s Sample Point can be anywhere inside the nominal
range of node A’s Phase Buffer Segments, so the bit transmitted by node B must arrive at node A before the start
of Phase_Seg1.
This condition defines the length of Prop_Seg.
If the edge from recessive to dominant transmitted by node B would arrive at node A after the start of Phase_Seg1,
it could happen that node A samples a recessive bit instead of a dominant bit, resulting in a bit error and the
destruction of the current frame by an error flag.
The error occurs only when two nodes arbitrate for the CAN bus that have oscillators of opposite ends of the
tolerance range and that are separated by a long bus line; this is an example of a minor error in the bit timing
configuration (Prop_Seg to short) that causes sporadic bus errors.
Some CAN implementations provide an optional 3 Sample Mode The ML9620 does not.
In this mode, the CAN
bus input signal passes a digital low-pass filter, using three samples and a majority logic to determine the valid bit
value.
This results in an additional input delay of 1 tq, requiring a longer Prop_Seg.
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