參數(shù)資料
型號(hào)： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 89/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-15
PLL Macro
The PLL functionality of the clock conditioning block is
supported by the PLL macro. Note that the PLL macro
reference clock uses the CLKA input of the CCC block,
which is only accessible from the global A[0:2] package
pins. Refer to Figure 2-14 on page 2-16 for more
information.
The PLL macro provides five derived clocks (three
independent) from a single reference clock. The PLL
macro also provides power-down input and lock output
signals.
See
for
more
information.
Inputs:
CLKA: selected clock input
POWERDOWN (active low): disables PLLs. The
default state is Powerdown On (active low).
Outputs:
LOCK: indicates that PLL output has locked on the
input reference signal
GLA, GLB, GLC: outputs to respective global
networks
YB, YC: allows output from the CCC to be routed
back to the FPGA core
As previously described, the PLL allows up to five flexible
and independently configurable clock outputs. Figure 2-18
on page 2-19 illustrates the various clock output options
and delay elements.
As illustrated, the PLL supports three distinct output
frequencies from a given input clock. Two of these (GLB
and GLC) can be routed to the B and C global network
access, respectively, and/or routed to the device core (YB
and YC).
There are five delay elements to support phase control
on all five outputs (GLA, GLB, GLC, YB, and YC).
There is also a delay element in the feedback loop that
can be used to advance the clock relative to the
reference clock.
The PLL macro reference clock can be driven by an INBUF*
macro to create a composite macro, where the I/O macro
drives the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be placed
in one of the dedicated global I/O locations.
The PLL macro reference clock can be driven directly
from the FPGA core.
The PLL macro reference clock can also be driven from an
I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro,
PLLINT,
to
differentiate
from
the
hardwired
I/O
connection described earlier.
The visual PLL configuration in SmartGen, part of the
Libero IDE and Designer tools, will derive the necessary
internal divider ratios based on the input frequency and
desired
output
frequencies
selected
by
the
user.
SmartGen also allows the user to select the various delays
and phase shift values necessary to adjust the phases
between the reference clock (CLKA) and the derived
clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows
the user to select the input clock source. SmartGen
automatically instantiates the special macro, PLLINT,
when needed.
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