參數(shù)資料
型號： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 118/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-41
Solution 4
5 V Output Tolerance
ProASIC3E I/Os must be set to 3.3 V LVTTL or 3.3 V
LVCMOS mode to reliably drive 5 V TTL receivers. It is also
critical that there be NO external I/O pull-up resistor to
5 V, since this resistor would pull the I/O pad voltage
beyond
the
3.6 V
absolute
maximum
value,
and
consequently cause damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode,
ProASIC3E I/Os can directly drive signals into 5 V TTL
receivers. In fact, VOL =0.4 V and VOH = 2.4 V in both
3.3 V LVTTL and 3.3 V LVCMOS modes exceeds the
VIL =0.8 V and VIH = 2 V level requirements of 5 V TTL
receivers. Therefore, level '1' and level '0' will be
recognized correctly by 5 V TTL receivers.
Figure 2-29 Solution 4
Table 2-19 Comparison Table for 5 V Compliant Receiver Scheme
Scheme
Board Components
Speed
Current Limitations
1
Two resistors
Low to High1
Limited by transmitter's drive strength
2
Resistor and Zener 3.3 V
Medium
Limited by transmitter's drive strength
3
Bus switch
High
N/A
4
Minimum resistor value2
R = 47
at T
J = 70°C
R = 150
at T
J = 85°C
R = 420
at T
J = 100°C
Medium
Maximum diode current at 100% duty cycle, signal constantly at '1'
5 × 52.7 mA at TJ = 70°C / 10-year lifetime
16.5 mA at TJ = 85°C / 10-year lifetime
5.9 mA at TJ = 100°C / 10-year lifetime
For duty cycles other than 100%, the currents can be increased by
a factor = 1/duty cycle.
Example: 20% duty cycle at 70°C
Maximum current = (1/0.2) × 52.7 mA = 4 × 52.7 mA = 263.5 mA
Notes:
1. Speed and current consumption increase as the board resistance values decrease.
2. Resistor values ensure I/O diode long term reliability.
Solution 4
2.5 V
5.5 V
On-Chip
Clamp
Diode
2.5 V
Requires one board resistor.
Available for LVCMOS 2.5 V / 5.0 V.
ProASIC3E I/O Input
Rext
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