參數(shù)資料
型號： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 39/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-65
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input
buffer clock delays, as these are I/O standard dependent and the clock may be driven and conditioned internally by the
CCC module. For more details on clock conditioning capabilities, please refer to the "Clock Conditioning Circuits"
section on page 2-13. Table 3-91, Table 3-92, and Table 3-93 on page 3-66 present minimum and maximum global clock
delays within the device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 3-91 A3PE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.83
1.04
0.94
1.18
1.11
1.39
1.33
1.67
ns
tRCKH
Input High Delay for Global Clock
0.81
1.06
0.93
1.21
1.09
1.42
1.31
1.71
ns
tRCKMPWH
Minimum Pulse Width High for Global
Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global
Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.25
0.28
0.33
0.40
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Table 3-92 A3PE1500 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
1.07
1.29
1.22
1.47
1.43
1.72
2.07
ns
tRCKH
Input High Delay for Global Clock
1.06
1.32
1.21
1.50
1.42
1.76
1.71
2.12
ns
tRCKMPWH
Minimum Pulse Width High for Global
Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global
Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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