參數(shù)資料
型號： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 131/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-53
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
DC
Don't Connect
This pin should not be connected to any signals on the
printed circuit board (PCB). These pins should be left un-
connected.
Software Tools
Overview of Tools Flow
The ProASIC3E family of FPGAs is fully supported by both
Actel Libero IDE and Designer FPGA Development
software. Actel Libero IDE is an integrated design
manager that seamlessly integrates design tools while
guiding the user through the design flow, managing all
design and log files, and passing necessary design data
among tools. Additionally, Libero IDE allows users to
integrate both schematic and HDL synthesis into a single
flow and verify the entire design in a single environment
(see the Libero IDE flow diagram located on the Actel
website).
Libero
IDE
includes
Synplify
AE
from
Synplicity, ViewDraw AE from Mentor Graphics,
ModelSim HDL Simulator from Mentor Graphics,
WaveFormer Lite AE from SynaptiCAD, PALACE AE
Physical Synthesis from Magma Design Automation,
and Designer software from Actel.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
Timer—a world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
NetlistViewer—a design netlist schematic viewer
ChipPlanner—a graphical floorplanner viewer and
editor
SmartPower—a tool that enables the designer to
quickly estimate the power consumption of a
design
PinEditor—a graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor—a tool that displays all
assigned and unassigned I/O macros and their
attributes in a spreadsheet format
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
core generator, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design.
Actel Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence. The Designer software is
available for both the Windows and UNIX operating
systems.
Programming
Programming can be performed using tools such as
Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel).
The user can generate *.stp programming files from the
Designer software and use these files to program a
device.
ProASIC3E devices can be programmed in system. For
more information on ISP of ProASIC3E devices, refer to
The ProASIC3E device can be serialized with a unique
identifier stored in the FlashROM of each device.
Serialization is an automatic assignment of serial
numbers that are stored within the STAPL file used for
programming. The area of the FlashROM used for
holding such identifiers is defined using SmartGen and
the range of serial numbers to be used is defined at the
time of STAPL file generation with FlashPoint. Serial
number values for STAPL file generation can even be
read from a file of predefined values. Serialized
programming using a serialized STAPL file can be done
through Actel In House Programming (IHP), an external
vendor using Silicon Sculptor software, or via the ISP
capabilities of the FlashPro software.
Security
ProASIC3E devices have a built-in 128-bit AES decryption
core. The decryption core facilitates secure, in-system
programming of the FPGA core array fabric and the
FlashROM. The FlashROM and the FPGA core fabric can
be
programmed
independently
from
each
other,
allowing the FlashROM to be updated without the need
for change to the FPGA core fabric. The AES master key is
stored in on-chip nonvolatile memory (Flash). The AES
master key can be preloaded into parts in a secure
programming environment (such as the Actel in-house
programming center) and then "blank" parts can be
shipped to an untrusted programming or manufacturing
center for final personalization with an AES encrypted
bitstream. Late stage product changes or personalization
相關(guān)PDF資料
PDF描述
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
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