參數(shù)資料
型號(hào)： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 138/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-3
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and
Industrial)
Sophisticated
power-up
management
circuitry
is
designed into every ProASIC3E device. These circuits
ensure easy transition from the powered-off state to the
powered-up state of the device. The many different
supplies can power-up in any sequence with minimized
current spikes or surges. In addition, the I/O will be in a
known state through the power-up sequence. The basic
principle is shown in Figure 3-1.
There are five regions to consider during power-up.
ProASIC3E I/Os are activated only if ALL of the following
three conditions are met:
1. VCC and VCCI are above the minimum specified trip
points (Figure 3-1).
2. VCCI > VCC - 0.75 V (Typical).
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV
higher than ramp-down trip points. This specifically
built-in
hysteresis
prevents
undesirable
power-up
oscillations and current surges. Note the following:
During programming, I/Os become tristated and
weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump
VPUMP supply have no influence on I/O behavior.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input
buffer activation.
Figure 3-1
I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs),
but slower because V
CCI
/V
CC
are below
specification. For the same reason, input
buffers do not meet V
IH
/V
IL
levels, and
output buffers do not meet V
OH
/V
OL
levels.
Min V
CCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON,
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, V
IH
/V
IL
, V
OH
/V
OL
, etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because V
CCI is
below specification. For the
same reason, input buffers do not
meet V
IH
/V
IL
levels, and output
buffers do not meet V
OH
/V
OL
levels.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the V
CC
is below specification.
V
CC = VCCI + VT
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