參數(shù)資料
型號： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 27/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
3- 54
Advanced v0.5
Output Register
Timing Characteristics
Figure 3-27 Output Register Timing Diagram
Preset
Clear
DOUT
CLK
Data_out
Enable
tOSUE
50%
tOSUD tOHD
50%
tOCLKQ
1
0
tOHE
tORECPRE
t
OREMPRE
tORECCLR
tOREMCLR
tOWCLR
tOWPRE
tOPRE2Q
tOCLR2Q
tOCKMPWHtOCKMPWL
50%
Table 3-83 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tOCLKQ
Clock-to-Q of the Output Data Register
0.63
0.71
0.84
1.01
ns
tOSUD
Data Setup time for the Output Data Register
0.43
0.49
0.57
0.69
ns
tOHD
Data Hold time for the Output Data Register
0.00
ns
tOSUE
Enable Setup time for the Output Data Register
0.43
0.49
0.57
0.69
ns
tOHE
Enable Hold time for the Output Data Register
0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
0.63
0.71
0.84
1.01
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
0.45
0.51
0.60
0.72
ns
tOREMCLR
Asynchronous Clear Removal time for the Output Data Register
0.00
ns
tORECCLR
Asynchronous Clear Recovery time for the Output Data Register
0.22
0.25
0.30
0.36
ns
tOREMPRE
Asynchronous Preset Removal time for the Output Data Register
0.00
ns
tORECPRE
Asynchronous Preset Recovery time for the Output Data Register
0.22
0.25
0.30
0.36
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.25
0.28
0.33
0.40
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.25
0.28
0.33
0.40
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.36
0.41
0.48
0.58
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.41
0.46
0.54
0.65
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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