參數(shù)資料
型號： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 147/168頁
文件大小： 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
1- 2
A dvanced v0. 5
Live at Power-Up
The Actel Flash-based ProASIC3E devices support Level 0
of the live at power-up (LAPU) classification standard.
This feature helps in system component initialization,
execution of critical tasks before the processor wakes up,
setup and configuration of memory blocks, clock
generation, and bus activity management. The LAPU
feature
of
Flash-based
ProASIC3E
devices
greatly
simplifies total system design and reduces total system
cost,
often
eliminating
the
need
for
Complex
Programmable
Logic
Devices
(CPLDs)
and
clock
generation PLLs that are used for this purpose in a
system. In addition, glitches and brownouts in system
power will not corrupt the ProASIC3E device's Flash
configuration, and unlike SRAM-based FPGAs, the device
will not have to be reloaded when system power is
restored. This enables the reduction or complete removal
of the configuration PROM, expensive voltage monitor,
brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC3E devices simplify
total system design, and reduce cost and design risk,
while increasing system reliability and improving system
initialization time.
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of ProASIC3E
Flash-based FPGAs. Once it is programmed, the Flash cell
configuration element of ProASIC3E FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based
ProASIC3E
devices
exhibit
power
characteristics similar to an ASIC, making them an ideal
choice
for
power-sensitive
applications.
ProASIC3E
devices have only a very limited power-on current surge,
and no high-current transition period, both of which
occur on many FPGAs.
ProASIC3E
devices also
have
low
dynamic
power
consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3E family offers many benefits, including
nonvolatility
and
reprogrammability
through
an
advanced Flash-based, 130-nm LVCMOS process with
seven layers of metal. Standard CMOS design techniques
are used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
Advanced Architecture
The
proprietary
ProASIC3E
architecture
provides
granularity comparable to standard-cell ASICs. The
ProASIC3E
device
consists
of
five
distinct
and
programmable architectural features (Figure 1-1 on page
1-3):
FPGA VersaTiles
Dedicated FlashROM memory
Dedicated SRAM/FIFO memory
Extensive clock conditioning circuitry (CCC) and
PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic
function or as a D-flip-flop (with or without enable), or
as a latch by programming the appropriate Flash switch
interconnections. The versatility of the ProASIC3E core
tile
as
either
a
three-input
look-up-table
(LUT)
equivalent or as a D-flip-flop/latch with enable allows for
efficient use of the FPGA fabric. The VersaTile capability
is unique to the Actel ProASIC families of Flash-based
FPGAs. VersaTiles are connected with any of the four
levels of routing hierarchy. Flash switches are distributed
throughout
the
device
to
provide
nonvolatile,
reconfigurable interconnect programming. Maximum
core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry
allows for rapid, single-voltage (3.3 V) programming of
the ProASIC3E devices via an IEEE 1532 JTAG interface.
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