- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180243 > M7A3PE600-FPQ208I FPGA, 600000 GATES, PQFP208 PDF資料下載
參數(shù)資料
| 型號： | M7A3PE600-FPQ208I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PQFP208 |
| 封裝： | 0.50 MM PITCH, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 101/168頁 |
| 文件大小： | 1335K |
| 代理商： | M7A3PE600-FPQ208I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁當(dāng)前第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁
ProASIC3E Flash Family FPGAs
2- 26
Advanced v0.5
Signal Descriptions for FIFO4K18
The following signals are used to configure the FIFO4K18
memory element:
WW and RW
These signals enable the FIFO to be configured in one of
the five allowable aspect ratios (Table 2-9).
WBLK and RBLK
These signals are active low and will enable the
respective ports when low. When the RBLK signal is high,
that port’s outputs hold the previous value.
WEN and REN
Read and write enables. WEN is active low and REN is
active high by default. These signals can be configured as
active high or low.
WCLK and RCLK
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
RPIPE
This signal is used to specify pipelined read on the
output. A low on RPIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A high indicates a pipelined read, and data
appears on the output in the next clock cycle.
RESET
This active low signal resets the control logic and forces
the output hold state registers to zero when asserted. It
does not reset the contents of the memory array
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous RESET
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning
with
for
the
specifications.
WD
This is the input data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. When a data width
less than 18 is specified, unused higher-order signals
must be grounded (Table 2-10).
RD
This is the output data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. Like the WD bus, high-
order bits become unusable if the data width is less than
18. The output data on unused pins is undefined
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further
counting once the FIFO is empty (i.e., the Empty flag
goes high). A high on this signal inhibits the counting.
FSTOP is used to stop the FIFO write counter from further
counting once the FIFO is full (i.e., the Full flag goes
high). A high on this signal inhibits the counting.
For more information on these signals, refer to the
FULL, EMPTY
When the FIFO is full and no more data can be written,
the Full flag asserts high. The Full flag is synchronous to
WCLK to inhibit writing immediately upon detection of a
full condition and to prevent overflows. Since the write
address is compared to a resynchronized (and thus time-
delayed) version of the read address, the Full flag will
remain asserted until two WCLK active edges after a read
operation eliminates the full condition.
When the FIFO is empty and no more data can be read,
the Empty flag asserts high. The Empty flag is
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
underflows. Since the read address is compared to a
resynchronized (and thus time-delayed) version of the
write address, the Empty flag will remain asserted until
two RCLK active edges, after a write operation removes
the empty condition.
For more information on these signals, refer to the "FIFO
AFULL, AEMPTY
These are programmable flags and will be asserted on
the
threshold
specified
by
AFVAL
and
AEVAL,
respectively.
When the number of words stored in the FIFO reaches
the amount specified by AEVAL while reading, the
Table 2-9 Aspect Ratio Settings for WW[2:0]
WW[2:0]
RW[2:0]
DxW
000
4kx1
001
2kx2
010
1kx4
011
512x9
100
256x18
101, 110, 111
Reserved
Table 2-10 Input Data Signal Usage for Different Aspect
Ratios
DxW
WD/RD Unused
4kx1
WD[17:1], RD[17:1]
2kx2
WD[17:2], RD[17:2]
1kx4
WD[17:4], RD[17:4]
512x9
WD[17:9], RD[17:9]
256x18
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3PE600-FPQG208I | FPGA, 600000 GATES, PQFP208 |
| M7R-R63FAJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT |
| M7R-R68TAJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT |
| M7R76FCJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS OUTPUT |
| M7R-R53FCJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。