參數(shù)資料
型號： M7A3PE600-FFG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, FBGA-484
文件頁數(shù)： 37/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG484I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-63
Timing Characteristics
Figure 3-36 Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
t
SUE
50%
t
SUD
t
HD
50%
t
CLKQ
0
t
HE
t
RECPRE
t
REMPRE
tRECCLR
t
REMCLR
t
WCLR
t
WPRE
t
PRE2Q
t
CLR2Q
t
CKMPWH tCKMPWL
50%
Table 3-90 Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tCLKQ
Clock-to-Q of the Core Register
0.54
0.61
0.72
0.86
ns
tSUD
Data Setup time for the Core Register
0.40
0.46
0.54
0.65
ns
tHD
Data Hold time for the Core Register
0.00
ns
tSUE
Enable Setup time for the Core Register
0.43
0.49
0.57
0.69
ns
tHE
Enable Hold time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.40
0.45
0.53
0.64
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.40
0.45
0.53
0.64
ns
tREMCLR
Asynchronous Clear Removal time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery time for the Core Register
0.22
0.25
0.30
0.36
ns
tREMPRE
Asynchronous Preset Removal time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery time for the Core Register
0.22
0.25
0.30
0.36
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.25
0.28
0.33
0.40
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.25
0.28
0.33
0.40
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.36
0.41
0.48
0.58
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.41
0.46
0.54
0.65
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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