參數(shù)資料
型號(hào)： M7A3PE600-FFG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, FBGA-484
文件頁(yè)數(shù)： 113/168頁(yè)
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG484I
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ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-37
Grounds
Powers
I/Os and other pins
Cold-Sparing Support
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
ProASIC3E devices support cold-sparing for all I/O
configurations. Standards such as PCI which require I/O
clamp diodes can also achieve cold-sparing compliance,
since clamp diodes get disconnected internally when the
supplies are at 0 V.
If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitor is
in parallel with this resistor). The RC time constant
should ensure full discharge of supplies before cold-
sparing functionality is required. The resistor is necessary
to ensure that the power pins are discharged to ground
every time there is an interruption of power to the
device.
Electrostatic Discharge (ESD) Protection
ProASIC3E devices are tested per JEDEC Standard
JESD22-A114-B.
ProASIC3E devices contain clamp diodes at every I/O,
global, and power pad. Clamp diodes protect all device
pads against damage from ESD as well as from excessive
voltage transients.
ProASIC3E devices are tested to the following models:
Human Body Model (HBM) with a tolerance of 2,000 V,
the Machine Model (MM) with a tolerance of 250 V, and
the Charged Device Model (CDM) with a tolerance of
200 V.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND, and its N side connected to the
pad. During operation, these diodes are normally
biased in the Off state, except when transient voltage is
significantly above VCCI or below GND levels.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-18 for more
information about the I/O standards and the clamp
diode.
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
Table 2-18 I/O Hot-Swap and 5 V Input Tolerance Capabilities
I/O Assignment
Clamp
Diode
Hot
Insertion
5 V Input
Tolerance Input Buffer
Output
Buffer
3.3 V LVTTL/LVCMOS
No
Yes
Yes1
Enabled/Disabled
3.3 V PCI, 3.3 V PCI-X
Yes
No
Yes1
Enabled/Disabled
LVCMOS 2.5 V 3
No
Yes
No
Enabled/Disabled
LVCMOS 2.5 V / 5.0 V 3
Yes
No
Yes2
Enabled/Disabled
LVCMOS 1.8 V
No
Yes
No
Enabled/Disabled
LVCMOS 1.5 V
No
Yes
No
Enabled/Disabled
Voltage-Referenced Input Buffer
No
Yes
No
Enabled/Disabled
Differential, LVDS/BLVDS/M-LVDS/LVPECL
No
Yes
No
Enabled/Disabled
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. In the SmartGen Core Reference Guide, select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25
macro for the LVCMOS 2.5 V I/O standard.
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