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參數(shù)資料
| 型號： | M7A3PE600-FFG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 2/168頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | M7A3PE600-FFG484I |
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ProASIC3E Flash Family FPGAs
1- 4
A dvanced v0. 5
VersaTiles
The ProASIC3E core consists of VersaTiles, which have been enhanced from the ProASICPLUS core tiles. The ProASIC3E
VersaTile supports the following:
All three-input logic functions – LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-2 for VersaTile configurations.
For more information about VersaTiles, refer to the "VersaTile" section on page 2-2.
User Nonvolatile FlashROM
Actel ProASIC3E devices have 1 kbit of on-chip, user-
accessible, nonvolatile FlashROM. The FlashROM can be
used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example,
set-top boxes)
Secure key storage for secure communications
algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard ProASIC3E
IEEE 1532 JTAG programming interface. The core can be
individually programmed (erased and written), and on-
chip AES decryption can be used selectively to securely
load data over public networks, such as security keys
stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG
programming interface, and its contents can be read
back either through the JTAG programming interface or
via direct FPGA core addressing. Note that the FlashROM
can ONLY be programmed from the JTAG interface, and
cannot be programmed from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits;
however, reading is performed on a byte-by-byte basis
using synchronous interface. A 7-bit address from the
FPGA core defines which of the 8 banks and which of the
16 bytes within that bank are being read. The three most
significant
bits
(MSBs)
of
the
FlashROM
address
determine the bank, and the four least significant bits
(LSBs) of the FlashROM address define the byte.
The Actel ProASIC3E development software solutions,
Libero
Integrated
Design
Environment
(IDE)
and
Designer v6.1 or later, have extensive support for the
FlashROM memory. One such feature is auto-generation
of
sequential
programming
files
for
applications
requiring a unique serial number in each part. The
second part allows the inclusion of static data for system
version control. Data for the FlashROM can be generated
quickly and easily using Actel Libero IDE and Designer
software
tools.
Comprehensive
programming
file
support is also included to allow for easy programming
of large numbers of parts with differing FlashROM
contents.
SRAM and FIFO
ProASIC3E devices have embedded SRAM blocks along
the north and south sides of the device. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256x18, 512x9, 1kx4, 2kx2, or
4kx1 bits. The individual blocks have independent read
and write ports that can be configured with different bit
widths on each port. For example, data can be sent
through a 4-bit port and read as a single bitstream. The
embedded SRAM blocks can be initialized via the device
JTAG port (ROM emulation mode), using the UJTAG
macro. For more information, refer to the application
Figure 1-2 VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3PE600-FFGG256I | FPGA, 600000 GATES, PBGA256 |
| M7A3PE600-FFGG484I | FPGA, 600000 GATES, PBGA484 |
| M7A3PE600-FPQ208I | FPGA, 600000 GATES, PQFP208 |
| M7A3PE600-FPQG208I | FPGA, 600000 GATES, PQFP208 |
| M7R-R63FAJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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