參數(shù)資料
型號： M7A3PE600-FFG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, FBGA-484
文件頁數(shù)： 153/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG484I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-17
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 3-15 Summary of AC Measuring Points
Standard
Input Reference Voltage
(VREF_TYP)
Board Termination
Voltage (VTT_REF)
Measuring Trip Point (Vtrip)
3.3 V LVTTL/3.3 V LVCMOS
–
1.4 V
2.5 V LVCMOS
–
1.2 V
1.8 V LVCMOS
–
0.90 V
1.5 V LVCMOS
–
0.75 V
3.3 V PCI
–
0.285 * VCCI (RR)
0.615 * VCCI (FF))
3.3 V PCI-X
–
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V GTL
0.8 V
1.2 V
VREF
2.5 V GTL
0.8 V
1.2 V
VREF
3.3 V GTL+
1.0 V
1.5 V
VREF
2.5 V GTL+
1.0 V
1.5 V
VREF
HSTL (I)
0.75 V
VREF
HSTL (II)
0.75 V
VREF
SSTL2 (I)
1.25 V
VREF
SSTL2 (II)
1.25 V
VREF
SSTL3 (I)
1.5 V
1.485 V
VREF
SSTL3 (II)
1.5 V
1.485 V
VREF
LVDS
–
Cross point
LVPECL
–
Cross point
Table 3-16 I/O AC Parameter Definitions
Parameter
Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer with Schmitt Trigger disabled
tDOUT
Data to Output Buffer delay through the I/O interface
tEOUT
Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN
Input Buffer to Data delay through the I/O interface
tPYS
Pad to Data delay through the Input Buffer with Schmitt Trigger enabled
tHZ
Enable to Pad delay through the Output Buffer—high to Z
tZH
Enable to Pad delay through the Output Buffer—Z to high
tLZ
Enable to Pad delay through the Output Buffer—low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to low
tZHS
Enable to Pad delay through the Output Buffer with delayed enable—Z to high
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to low
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