參數(shù)資料
型號(hào)： M58MR064D100ZC6T
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 399K
代理商： M58MR064D100ZC6T
M58MR064C, M58MR064D
24/52
COMMON FLASH INTERFACE (CFI)
The Common Flash Interface (CFI) specification is
a JEDEC approved, standardized data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 17, 18, 19, 20, 21, 22 and 23 show the ad-
dress used to retrieve each data. The CFI data
structure gives information on the device, such as
the sectorization, the command set and some
electrical specifications. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number is written, starting at
address 81h. This area can be accessed only in
read mode and there are no ways of changing the
code after it has been written by ST. Write a read
instruction to return to Read mode (see Table 11).
Refer to the CFI Query instruction to understand
how the M58MR064 enters the CFI Query mode.
Table 17. Query Structure Overview
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs.
Table 18. CFI Query Identification String
Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’.
1. DRC means Die Revision Code.
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
80h
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
Offset
Sub-section Name
Description
Value
00h
0020h
Manufacturer Code
ST
01h
88DCh
88DDh
Device Code
Top
Bottom
02h
reserved
Reserved
03h
DRC (1)
Die Revision Code
04h-0Fh
reserved
Reserved
10h
0051h
Query Unique ASCII String "QRY"
"Q"
11h
0052h
"R"
12h
0059h
"Y"
13h
0003h
Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
14h
0000h
15h
offset = P = 0039h
Address for Primary Algorithm extended Query table (see Table 20)
p = 39h
16h
0000h
17h
0000h
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported (note: 0000h means
none exists)
NA
18h
0000h
19h
value = A = 0000h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
1Ah
0000h
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M58MR064C120ZC6T 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58MR064D120ZC6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58MR064DZC 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58MR064-ZCT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58PR001LE 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:512-Mbit or 1-Gbit (】 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
M58PR001LE96ZAC5 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:512-Mbit or 1-Gbit (】 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
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