參數(shù)資料
型號(hào)： M58MR064D100ZC6T
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù)： 13/52頁(yè)
文件大?。?/td> 399K
代理商： M58MR064D100ZC6T
M58MR064C, M58MR064D
20/52
Power-down configuration (CR10). The RP pin
may be configured to give very low power con-
sumption when driven low (power-down state). In
power-down the ICC supply current is reduced to a
typical figure of ICC2; if this function is disabled
(default at power-up) the RP pin causes only a re-
set of the device and the supply current is the
stand-by value. The recovery time after a RP pulse
is significantly longer when power-down is en-
abled (see Table 31).
Wait configuration (CR8). In burst mode WAIT
indicates whether the data on the output bus are
valid or a wait state must be inserted. The config-
uration bit determines if WAIT will be asserted one
clock cycle before the wait state or during the wait
state (see Figure 7). WAIT is asserted during a
continuous burst and also duringa4or 8 burst
length if no-wrap configuration is selected.
Burst order configuration (CR7) and Burst
Wrap configuration (CR3). See Table 16 for
burst order and length.
Clock configuration (CR6). In burst mode deter-
mines if address is latched and data is output on
the rising or falling edge of the clock.
Burst length (CR2-CR0). In burst mode deter-
mines the number of words output by the memory.
It is possible to have 4 words, 8 words or a contin-
uous burst mode, in which all the words are read
sequentially. In continuous burst mode the burst
sequence can cross the end of each of the two
banks (all banks in read array mode). In continu-
ous burst mode or in 4, 8 words no-wrap it may
happen that the memory will stop the data output
flow for a few clock cycles; this event is signaled by
WAIT going low until the output flow is resumed.
The initial address determines if the output delay
will occur as well as its duration. If the starting ad-
dress is aligned to a four words boundary no wait
states will be needed. If the starting address is
shifted by 1,2 or 3 positions from the four word
boundary, WAIT will be asserted for 1, 2 or 3 clock
cycles when the burst sequence is crossing the
first 64 word boundary. WAIT will be asserted only
once during a continuous burst access. See also
Table 16.
Figure 6. X-Latency Configuration Sequence
AI90092
A21-A16
VALID ADDRESS
K
L
ADQ15-ADQ0
VALID ADDRESS
VALID DATA
ADQ15-ADQ0
VALID ADDRESS
VALID DATA
ADQ15-ADQ0
VALID ADDRESS
VALID DATA
CONFIGURATION CODE 4
CONFIGURATION CODE 3
CONF. CODE 2
VALID DATA
相關(guān)PDF資料
PDF描述
M58MR064C120ZC6T 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58MR064D120ZC6T 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M59MR032C100ZC6T 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M59MR032D100ZC6T 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M59MR032C120ZC6T 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58MR064D120ZC6T 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58MR064DZC 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58MR064-ZCT 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
M58PR001LE 制造商:NUMONYX 制造商全稱(chēng):Numonyx B.V 功能描述:512-Mbit or 1-Gbit (】 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
M58PR001LE96ZAC5 制造商:NUMONYX 制造商全稱(chēng):Numonyx B.V 功能描述:512-Mbit or 1-Gbit (】 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
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