參數(shù)資料
型號： M37754S4CHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
中文描述： 單芯片16位微機的CMOS
文件頁數(shù)： 92/114頁
文件大小： 1116K
代理商： M37754S4CHP
92
PRELIMINARY
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5
×
10
9
f(X
IN
)
5
×
10
9
f(X
IN
)
4
×
10
9
f(X
IN
)
Bus timing data formulas
Memory expansion and Microprocessor mode : Low-speed running
(V
CC
= 5 V±10 %, V
SS
= 0 V, T
a
= –20 to 85 °C, f(X
IN
)
≤
25 MHz when
the clock source select bit = “0”
, unless otherwise noted)
t
su(A–DL/DH)
t
su(CS–DL/DH)
t
w(
φ
H)
, t
w(
φ
L)
t
w(WR)
, t
w(RD)
t
d(A–WR)
t
d(A–RD)
t
d(A–ALE)
t
d(BHE–WR)
t
d(BHE–RD)
t
d(BHE–ALE)
t
d(CS–WR)
t
d(CS–RD)
t
d(CS–ALE)
t
w(ALE)
t
h(WR–A)
t
h(RD–A)
t
d(WR–BHE)
t
d(RD–BHE)
t
d(WR–CS)
Symbol
Data setup time with address stabilized
Data setup time with chip select stabilized
φ
high-level pulse width, f low-level pulse width
WR, RD low-level pulse width
Address output delay time
Address output delay time
Address output delay time
____
____
____
Chip select output delay time
Chip select output delay time
Chip select output delay time
ALE pulse width
Address hold time
Address hold time
____
____
Chip select hold time
Chip select holt time
Data hold time
Floating start delay time
Data setup time with address stabilized
Address output delay time
Address output delay time
Address output delay time
Address hold time
Floating release delay time
Parameter
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
2
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
2-
φ
access
– 60
– 60
– 20
– 20
– 25
– 25
– 32
– 25
– 25
– 32
– 25
– 25
– 32
– 18
– 30
– 30
– 30
– 30
– 30
– 30
– 25
– 10
– 65
– 28
– 28
– 35
– 22
– 60
– 60
– 20
3-
φ
access
Unit
– 60
– 60
– 25
– 25
– 65
– 25
– 25
– 65
– 25
– 25
– 65
– 18
4-
φ
access
7
×
10
9
f(X
IN
)
7
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
2
×
10
9
f(X
IN
)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
d(RD–CS)
t
h(WR–DLQ/DHQ)
t
pxz(WR–DLZ/DHZ)
t
su(LA–DL)
t
d(LA–WR)
t
d(LA–RD)
t
d(LA–ALE)
t
h(ALE–LA)
t
pzx(RD–DLZ)
8
: f(X
IN
)
≤
12.5 MHz when the clock source select bit = “1”
Note:
When the clock source select bit is “1”, regard f(X
IN
) in tables as 2·f(X
IN
).
– 65
5
×
10
9
f(X
IN
)
7
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
3
×
10
9
f(X
IN
)
2
×
10
9
f(X
IN
)
1
×
10
9
f(X
IN
)
– 65
– 28
– 28
– 28
– 15
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