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參數(shù)資料
| 型號： | M37754S4CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機的CMOS |
| 文件頁數(shù)： | 18/114頁 |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754S4CHP |
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 2 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and is
DBC is an interrupt used during debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 3 shows the
addresses of the interrupt control registers and Figure 10 shows the
bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
____
4
to INT
0
are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
In the INT
3
external interrupt, the INT
3
input, KI
3
to KI
0
inputs, or KI
4
to KI
0
inputs can be selected with bits 7 and 6 of INT
3
interrupt con-
trol register.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused simul-
taneously is partially fixed by hardware, but, it can also be adjusted
by software as shown in Figure 11.
The hardware priority is fixed as the following:
reset > DBC > watchdog timer > other interrupts
Table 2. Interrupt types and the interrupt vector addresses
Interrupts
____
4
external interrupt
____
3
external interrupt
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
____
2
external interrupt
____
1
external interrupt
____
0
external interrupt
____
Break instruction
Zero divide
Reset
Vector addresses
00FFD2
16
00FFD3
16
00FFD4
16
00FFD5
16
00FFD6
16
00FFD8
16
00FFDA
16
00FFDC
16
00FFDE
16
00FFE0
16
00FFE2
16
00FFE4
16
00FFE6
16
00FFE8
16
00FFEA
16
00FFEC
16
00FFEE
16
00FFF0
16
00FFF2
16
00FFF4
16
00FFF6
16
00FFF8
16
00FFFA
16
00FFFC
16
00FFFE
16
00FFD7
16
00FFD9
16
00FFDB
16
00FFDD
16
00FFDF
16
00FFE1
16
00FFE3
16
00FFE5
16
00FFE7
16
00FFE9
16
00FFEB
16
00FFED
16
00FFEF
16
00FFF1
16
00FFF3
16
00FFF5
16
00FFF7
16
00FFF9
16
00FFFB
16
00FFFD
16
00FFFF
16
Fig. 10 Interrupt control register bit configuration
7
6
5
4
3
2
1
0
Interrupt priority level
Interrupt request bit
(Note 1)
0 : No interrupt
1 : Interrupt
7
6
5
4
3
2
1
0
Interrupt priority level
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity select bit
0 : Set interrupt request bit at “H” level for level sense and when changing from “H” to “L”
level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing from “L” to “H”
level for edge sense.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Key input interrupt select bits 1, 0 (only for INT
3
interrupt control register)
0 0 : INT
3
interrupt selected
0 1 : Do not select.
1 0 : Key input interrupt (KI
3
to KI
0
) selected
1 1 : Key input interrupt (KI
4
to KI
0
) selected
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2.
Note 1:
The A-D conversion interrupt request bit becomes undefined after reset. Clear this bit to “0” before use of the A-D conversion interrupt.
Interrupt control register configuration for INT
4
– INT
0
(Note 2)
.
Note 2:
The contents of INT
4
interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see
Figure 15) is set to “1.”
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