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參數(shù)資料
| 型號(hào)： | M37754S4CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機(jī)的CMOS |
| 文件頁數(shù)： | 12/114頁 |
| 文件大小： | 1116K |
| 代理商： | M37754S4CHP |
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 5 shows basic waveforms of the bus interface unit. The RD
signal becomes “L” when the bus interface unit reads an instruction
code or data from memory. The WR signal becomes “L” when the
bus interface unit writes data to memory.
Waveforms (1) and (3) in Figure 5 are used to access a single byte
or two bytes simultaneously. To read or write two bytes simulta-
neously, the first address accessed must be even. Furthermore,
when accessing an external memory area in memory expansion
mode or microprocessor mode, set the bus width select input pin
(BYTE) to “L” (external data bus width = 16 bits). The internal
memory area is always treated as 16-bit bus width regardless of
BYTE.
When performing 16-bit data read or write, if the conditions for simul-
taneously accessing two bytes are not satisfied, waveforms (2) and
(4) are used to access each byte, one by one.
However, when prefetching the instruction code, if the address of the
instruction code is odd, only one byte is read in the instruction queue
buffer.
Fig. 5 Basic waveforms of bus interface unit
(3)
(4)
(1)
(2)
WR
RD
Internal address
bus
(A
0
– A
23
)
Internal data bus
(D
0
– D
7
)
Internal data bus
(D
8
– D
15
)
Address
Data (even)
Data (odd)
WR
RD
Internal address
bus
(A
0
– A
23
)
Internal data bus
(D
0
– D
7
)
Internal data bus
(D
8
– D
15
)
Address
Data (even)
Data (odd)
WR
RD
Internal address
bus
(A
0
– A
23
)
Internal data bus
(D
0
– D
7
)
Internal data bus
(D
8
– D
15
)
Address (odd)
Address (even)
Address (odd)
Address (even)
Invalid data
Data (odd)
WR
RD
Internal address
bus
(A
0
– A
23
)
Internal data bus
(D
0
– D
7
)
Internal data bus
(D
8
– D
15
)
Invalid data
Data (odd)
Data (even)
Invalid data
Data (even)
Invalid data
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