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參數(shù)資料
| 型號： | M37754S4CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機(jī)的CMOS |
| 文件頁數(shù)： | 51/114頁 |
| 文件大小： | 1116K |
| 代理商： | M37754S4CHP |
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51
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Register
A-D control register 1
Chip select area register
Particular function select register 0
Particular function select register 1
Address
1F
16
63
16
6C
16
6D
16
Bit
5
2, 5, 6, 7
0, 1, 5, 6
2, 3, 4
Register
Waveform output mode register
Dead-time timer
Pulse output data register 1
Pulse output data register 0
____
4
interrupt control register
Address
1A
16
1B
16
1C
16
1D
16
45
16
6E
16
Notes 1:
Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to “1.”
2:
After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset.
3:
Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7.
Transmit clock output pin select bit
00 : Normal mode (output only to CLK
0
)
01 : Plural clocks specified; output to CLK
0
10 : Plural clocks specified; output to CLKS
0
11 : Plural clocks specified; output to CLKS
1
Internal clock stop select bit at WIT
(Note 1)
0 : Clock for peripheral function and watchdog timer are operating at WIT
1 : Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT
7
6
5
4
3
2
1
0
Particular function select register 1 (6D
16
)
Watchdog timer’s select bit
(Note 1)
0 : Exclusive clock deviding circuit output (Wf
512
, Wf
32
) is used as clock for watchdog
timer. Clock (Wf
512
, Wf
32
) for watchdog timer does not change in hold.
1 : Clock for peripheral device deviding circuit output (Pf
512
, Pf
32
) is used as clock for
watchdog timer. Clock (Pf
512
, Pf
32
) for watchdog timer changes in hold.
Watchdog timer exclusive clock dividing circuit is stopped.
Signal output stop select bit
(Note 1)
Refer to Table 8.
Expansion function select bit
(Note 2)
Refer to Figure 62.
Pull-up select bit 0
(Note 3)
0 : With no pull-up for P5
7
, P5
6
, P5
5
, P5
4
1 : With pull-up for P5
7
, P5
6
, P5
5
, P5
4
Pull-up select bit 1
(Note 3)
0 : With no pull-up for P9
5
1 : With pull-up for P9
5
TC
1
TC
0
Control bits affected by expansion
function select bit
Control registers affected by expansion
function select register
Fig. 63 Particular function select register 1 bit configuration
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