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參數(shù)資料
| 型號(hào)： | M37754S4CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機(jī)的CMOS |
| 文件頁數(shù)： | 28/114頁 |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754S4CHP |
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28
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ig-
nored. Note that bits 5, 6, and 7 of the up-down register (44
16
) are
the two-phase pulse signal processing select bits for timers A2, A3
and A4 respectively. Each timer operates in normal event counter
mode when the corresponding bit is “0” and performs two-phase
pulse signal processing when it is “1”.
Count is started by setting the count start bit to “1”. Data write and
read are performed in the same way as for normal event counter
mode. Note that the direction register of the input port must be set to
input mode because two kinds of pulse signals, described above, are
input. Also, there can be no pulse output in this mode.
Data write and data read are performed in the same way as for timer
mode. That is, when data is written to timer Ai halted, it is also written
to the reload register and the counter. When data is written to timer
Ai which is busy, the data is written to the reload register, but not to
the counter. The counter is reloaded with new data from the reload
register at the next reload time. The counter can be read at any time.
Two-phase pulse processing
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two kinds of pulses of
which phases differ by 90° to timer A2, A3, or A4. There are two types
of two-phase pulse processing operations. One uses timers A2 and
A3, and the other uses timer A4. In both processing operations, two
pulses described above are input to the TA
jOUT
(j = 2 to 4) pin and
TAj
IN
pin respectively.
When timers A2 and A3 are used, as shown in Figure 25, the count is
incremented when a rising edge is input to the TAk
IN
pin after the
level of TAk
OUT
(k=2,3) pin changes from “L” to “H”, and when the fall-
ing edge is input, the count is decremented.
For timer A4, as shown in Figure 26, when a phase-related pulse with
a rising edge input to the TA4
IN
pin is input after the level of TA4
OUT
pin changes from “L” to “H”, the count is incremented at the respec-
tive rising edge and falling edge of the TA4
OUT
pin and TA4
IN
pin.
When a phase-related pulse with a falling edge input to the TA4
OUT
pin is input after the level of TA4
IN
pin changes from “H” to “L”, the
count is decremented at the respective rising edge and falling edge
of the TA4
IN
pin and TA4
OUT
pin. When performing this two-phase
pulse signal processing, timer Aj mode register bit 0 and bit 4 must
Fig. 27 Timer Aj mode register bit configuration when performing
two-phase pulse signal processing in event counter mode
Fig. 25 Two-phase pulse processing operation of timers A2 and timer A3
Fig. 26 Two-phase pulse processing operation of timer A4
7 6 5 4 3 2 1 0
1
0
×
×
1
0
0
0
0 1 : Always “01” in event counter mode
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
×
×
: Not used in event counter mode
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
58
16
59
16
5A
16
TAk
OUT
TAk
IN
(k = 2, 3)
Increment-
count
Increment-
count
Increment-
count
Decrement-
count
Decrement-
count
Decrement-
count
TA4
OUT
TA4
IN
Decrement-count at each edge
Increment-count at each edge
Decrement-count at each edge
Increment-count at each edge
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