- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370849 > M37754S4CHP (Mitsubishi Electric Corporation) SINGLE-CHIP 16BIT CMOS MICROCOMPUTER PDF資料下載
參數(shù)資料
| 型號(hào)： | M37754S4CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機(jī)的CMOS |
| 文件頁(yè)數(shù)： | 49/114頁(yè) |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754S4CHP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)當(dāng)前第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
49
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmission
Transmission is started when bit 0 (TEj flag) of UARTj Transmit/Re-
ceive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and CTSj
input is “L”. As shown in Figure 60, data is output from T
X
Dj pin each
time when transmission clock CLKj changes from “H” to “L”. The data
is output from the least significant bit.
The TIj flag indicates whether the transmit buffer register is empty or
not. It is cleared to “0” when data is written in the transmit buffer reg-
ister and set to “1” when the contents of the transmit buffer register is
transferred to the transmit register.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmission start
condition is satisfied. If bit 2 of UARTj Transmit/Receive control reg-
ister 0 is “1”, CTSj input is ignored, and transmission start is con-
trolled only by the TEj flag and TIj flag. Once transmission has
started, the TEj flag, TIj flag, and CTSj signals are ignored until data
transmission completes. Therefore, transmission is not interrupt
when CTSj input is changed to “H” during transmission.
____
END
j signal (shown in Figure 60) is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIj flag is
cleared to “0” before theT
END
j signal goes “H”.
Bit 3 (T
X
EPTYj flag) of UARTj Transmit/Receive control register 0
changes to “1” at the next cycle just after the T
END
j signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission has completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit in
the UARTj transmit interrupt control register is set to “1”.
In only UART0, data can be output to a maximum of 3 external re-
ceive devices. This is realized under the condition in which the inter-
nal clock is selected and the transmission clock is output from one of
pins CLK
0
, CLKS
0
(multiplexed with R
X
D
0
) and CLKS
1
(multiplexed
with CTS
0
/RTS
0
). Make sure that do not switch the selection of the
clock during transmission. Figure 61 shows an external connection
example.
Plural output of transmit clock mode is set with bits 1 and 0 of the
particular function select register 1. Additionally, it is necessary to se-
lect the internal clock, disable CTS and RTS, receive and D-A output
with the UART0 Transmit/Receive mode register, UART0 Transmit/
Receive control registers 0 and 1, and A-D control register 1. Figure
62 shows the other registers bit configuration in plural output of trans-
mit clock mode and Figure 63 shows the particular function select
register 1 bit configuration .
Table 6 shows the function of the particular function select register
1’s bits 1 and 0, which is the output pin of transmit clock select bits:
TC
1
and TC
0
. According to this table, select the CLK
0
, CLKS
0
or
CLKS
1
pin corresponding to the contents of TC
1
and TC
0
, and out-
put the transmit clock.
Fig. 60 Clock synchronous serial I/O timing
Transmission
clock
TE
j
1/Pf
i
×
(n
+
1)
×
2
1/Pf
i
×
(n
+
1)
×
2
TI
j
CTS
j
Write in transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
Transmit register
←
Transmit buffer register
Stopped because TE
j
= “0”
CLK
j
T
ENDj
T
X
D
j
T
X
EPTY
j
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37754 | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| M37754M8C | Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī)) |
| M37902F8CHP | DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-23 3K/REEL |
| M37902FGCGP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FCCHP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3775PR-H400CL | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-0.75A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50B | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50C | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。