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參數(shù)資料
| 型號： | M37754S4CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機(jī)的CMOS |
| 文件頁數(shù)： | 61/114頁 |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754S4CHP |
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61
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 74 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf
32
/Pf
32
, which is obtained by di-
viding the peripheral devices’ clock Pf
2
by 16; or clock Wf
512
/Pf
512
,
which is obtained by doing it by 256. The watchdog timer frequency
select register shown in Figure 75 selects which clock is counted.
Wf
512
/Pf
512
is selected when its contents are “0”, and Wf
32/
Pf
32
is
selected when they are “1”. They are cleared to “0” after reset.
The watchdog timer clock select bit (bit 3 of particular function select
register 1; Figure 62) selects use of clock Wf
512
/Wf
32
or Pf
512
/Pf
32
as the clock source of watchdog timer. When selecting Wf
512
/Wf
32
,
the clock source of watchdog timer (Wf
512
/Wf
32
) is not active during
Hold state. When selecting Pf
512
/Pf
32
, the clock source of watchdog
timer (Pf
512
/Pf
32
) is active during Hold state, however, current con-
sumption can be reduced. It is because the Wf
512
/Wf
32
division cir-
cuit stops.
is set in the watchdog timer when “L” or 2Vcc is applied to the
______
RESET pin, STP instruction is executed, data is written to the watch-
dog timer, or the most significant bit of the watchdog timer becomes
“0”.
After FFF
16
is set in the watchdog timer, when the watchdog timer
counts the clock source by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF
16
is set again in the watchdog timer.
Normally, a program is written so that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program ex-
ecution and others, the most significant bit of the watchdog timer
becomes “0” and an interrupt is generated.
The microcomputer can be reset by writing “1” to bit 3 (software re-
set bit) of processor mode register 0 in the interrupt routine, de-
scribed in Figure 16 in the interrupt section, and generating a reset
pulse.
The watchdog timer stops its function when the RESET pin voltage
is raised to double the Vcc voltage.
The watchdog timer can also be used to return from when the clock
is stopped by the STP instruction. Refer to the section on the clock
generating circuit for more details.
The watchdog timer also becomes Hold state during Hold state and
the clock input to it is stopped.
______
Watchdog timer frequency select register
Watchdog timer clock select bit
Write to watchdog timer
STP instruction
S
R
Q
2Vcc
detection
Wachdog timer
Set FFF
16
RESET
1/16
1/16
Wf
32
Wf
512
Clock source for peripheral
devices
Pf
2
1/8
1/2
1/2
1/8
Pf
32
Pf
512
Pf
16
Hold request
Hold request
Address 60
16
Pf
16
STP return select bit
Fig. 74 Watchdog timer block diagram
7
6
5
4
3
2
1
0
0
Watchdog timer frequency
select register
0 : Wf
512
or Pf
512
selected
1 : Wf
32
or Pf
32
selected
This bit must be fixed to “0.”
Address
61
16
Fig. 75 Watchdog timer frequency select register bit configuration
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