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參數(shù)資料
| 型號： | K4N26323AE |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit GDDR2 SDRAM |
| 中文描述： | 128Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 12/52頁 |
| 文件大?。?/td> | 826K |
| 代理商： | K4N26323AE |
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- 12 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
Output Driver Strength Option
A
9
0
0
0
0
1
1
1
1
A
8
0
0
1
1
0
0
1
1
A
7
0
1
0
1
0
1
0
1
Ron[ohm]
60
55
50
45
40
35
30
25
The extended mode register stores the data output driver strength and on-die termination options. The
extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR2
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis-
ter). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are
written in the extended mode register. Four clock cycles are required to complete the write operation in the
extended mode register. 8 kinds of the output driver strength are supported by EMRS (A9, A8, A7) code. The
mode register contents can be changed using the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
DLL
A
6
0
1
DLL
DLLOFF
DLLON
EXTENDED MODE REGISTER SET(EMRS)
Address Bus
Extended
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
1
0
ODT.R
Output driver strength
DLL
DQS
A.L
ODT control
ODT option
Mode Register
OFF : On-die Termination of CMD
and ADDR pins on DRAM is off
X1 : On-die Termination value of
CMD and ADD pins are same as
the value of DQ
X2 : 2 times
of the value of DQ
X4 : 4 times
of the value of DQ
On-die Termination option
for CMD & ADDR
A
1
0
0
1
1
A
0
0
1
0
1
Value
OFF
X1
X2
X4
ODT of DQs @ RD
A
10
0
1
mode
ON
OFF
BA
0
0
1
A
n
~ A
0
MRS
EMRS
On-Die Termination Mode
A
3
0
0
1
1
A
2
0
1
0
1
Value
ODT OFF
ODT Cal. ON
Rterm=60
Rterm=120
*1. DLL control,ODT control,and ODT option command should be issued at low frequency clock(<100Mhz) with tIS/tIH=0.5tCK
*2. When single DQS is selected, 4 /DQS pins should be connected to VREF.
*1
*1
Additive Latency
A
4
0
1
Latency
0
1
*2
*1
DQS
A
5
0
1
DQS
Differential
Single
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