- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299200 > IDT71T75902S75BGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 1M X 18 ZBT SRAM, 7.5 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號： | IDT71T75902S75BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 ZBT SRAM, 7.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 25/26頁 |
| 文件大小： | 644K |
| 代理商： | IDT71T75902S75BGI8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁
6.42
8
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes(1)
Synchronous Truth Table(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/
LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/
W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (
CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When
CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires
CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/
W
CE1, CE2(5)
ADV/
LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L
Valid
External
X
LOAD WRITE
D
(7)
L
H
L
X
External
X
LOAD READ
Q
(7)
L
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
(Advance burst counter)
(2)
D
(7)
L
X
H
X
Internal
LOAD READ /
BURST READ
(Advance burst counter)(2)
Q
(7)
L
X
H
L
X
DESELECT or STOP(3)
HIZ
L
X
H
X
DESELECT / NOOP
NOOP
HIZ
H
X
SUSPEND
(4)
Previous Value
5319 tbl 08
OPERATION
R/
W
BW1
BW2
BW3(3)
BW4(3)
READ
H
XXXX
WRITE ALL BYTES
LLLL
L
WRITE BYTE 1 (I/O[0:7], I/OP1)
(2)
L
HHH
WRITE BYTE 2 (I/O[8:15], I/OP2)
(2)
LH
H
WRITE BYTE 3 (I/O[16:23], I/OP3)
(2,3)
LH
H
L
H
WRITE BYTE 4 (I/O[24:31], I/OP4)
(2,3)
L
HHH
L
NO WRITE
L
HHHH
5319 tbl 09
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
1
0
1
Second Address
0
1
0
1
0
Third Address
1
0
1
0
1
Fourth Address
(1)
111
00
1
0
5319 tbl 10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71V2558XS166BQ | 256K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
| IDT71V3576S133BGI | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
| IDT71V3576S133BQ | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
| IDT71V3576S133BQI | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
| IDT71V3576S133PFI | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71T75902S75PF | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71T75902S75PF8 | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71T75902S75PFG | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT71T75902S75PFG8 | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT71T75902S75PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18MBIT 7.5NS 100TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。