參數(shù)資料
型號(hào): ICS1531
英文描述: Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
中文描述: 三8位MSPS的的A / D轉(zhuǎn)換器與電源同步時(shí)鐘發(fā)生器
文件頁(yè)數(shù): 67/76頁(yè)
文件大?。?/td> 529K
代理商: ICS1531
Chapter 10
Timing Diagrams
ICS1531 Rev N 12/1/99
December, 1999
67
Copyright 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
10.3
AC Timing Diagrams
10.3.1
Phase-Locked-Loop Timing for Digital Setup and Hold
The input HSYNC signal is used to generate the REF output signal. In the Phase/Frequency Detector, the
REF signal is compared with ADCSYNC (which provides the recovered HSYNC signal).
Table 10-3
gives
the timing for these signals, and
Figure 10-5
shows timing characteristics.
Figure 10-5.
Timing for Phase-Locked Loop
Table 10-3.
Phase-Locked-Loop Timing
Time
Period
Timing Description
Min
Typ
Max
Units
t1
Input HSYNC Rise Time to
REF Rise Time
TBD
7
TBD
ns
Tp
Clock Period
ns
Td
Clock Duty Cycle
45-55
50-50
55-45
%
t2
ADCSYNC Active Time
4
×
Tp
ns
Tp
Input HSYNC Frequency
Result from:
Section 6.5.3, “Register 02h:
Fdbk Div 0 Register”
and
Section 6.5.4, “Register 03h:
Fdbk Div 1 Register”
=
Tp
Td
t1
HSYNC
CLK
ADCSYNC
t2
REF
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