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參數(shù)資料
| 型號： | ICS1531 |
| 英文描述： | Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator |
| 中文描述： | 三8位MSPS的的A / D轉(zhuǎn)換器與電源同步時鐘發(fā)生器 |
| 文件頁數(shù)： | 23/76頁 |
| 文件大?。?/td> | 529K |
| 代理商： | ICS1531 |
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Chapter 6
Register Set
ICS1531 Rev N 12/1/99
December, 1999
23
Copyright 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
Chapter 6
Register Set
The tables in this chapter detail the functionality of the bits in the ICS1531 Register Set. The tables include
the register locations, the bit positions, names, and definitions, along with their read/write access, reset
values, and any special functions or capabilities.
6.1
Reserved Bits
The ICS1531 has a number of reserved bits throughout the Register Set. These bits provide enhanced test
functions (intended for use only by ICS manufacturing) and calibration functions (intended for use in
production environments).
Important:
The customer must not change the value of reserved bits. If the customer changes the default
values of these reserved bits, normal operation of the ICS1531 can be affected.
6.2
Register Set Conventions
Register Set conventions include the following:
Bits are listed in the order of most-significant bit (MSB) to least-significant bit (LSB).
Unless otherwise indicated, bit settings are listed in terms of digital (and not hexadecimal) values.
When a bit definition includes word(s) in parentheses, the word in parenthesis is not part of the bit name,
but is given to explain the origin of the bit’s name.
6.3
Register Set Abbreviations and Acronyms
Table 6-1
lists and defines abbreviations and acronyms used specifically in this chapter. (
Table 1-1
lists
other abbreviations and acronyms used throughout this data sheet.)
Table 6-1.
Register Set Abbreviations and Acronyms
Abbreviation
or Acronym
Definition
D-DPA
Double-Buffered / Dynamic Phase Adjust.
Indicates double-buffered registers for which
working registers load during a software Dynamic Phase Adjust reset.
D-MK
Double-Buffered / Memory Clock.
Indicates double-buffered registers for which working
registers load during a software MCLK reset.
D-PK
Double-Buffered / Panel Clock.
Indicates double-buffered registers for which working registers
load during a software PNLCLK reset.
D-PLL
Double-Buffered / Phase-Locked Loop.
Indicates double-buffered registers for which working
registers load during a software pixel PLL reset.
IN-A
Increment All.
Indicates a value that increments with each all-layer revision of the ICS1531.
Reg
Register
R/W
Read/Write
Spec. Func.
Special Function.
Indicates a special function, such as the following (listed in this table):
D-DPA, D-MK, D-PK, D-PLL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1560M-001 | Video/Graphics Clock Generator |
| ICS1560M-003 | Video/Graphics Clock Generator |
| ICS1560N-001 | Video/Graphics Clock Generator |
| ICS1560N-003 | Video/Graphics Clock Generator |
| ICS1561AM-706 | Video/Graphics Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1532 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR |
| ICS1560M-001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1560M-003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1560N-001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1560N-003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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