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參數(shù)資料
| 型號： | ICS1531 |
| 英文描述： | Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator |
| 中文描述： | 三8位MSPS的的A / D轉(zhuǎn)換器與電源同步時鐘發(fā)生器 |
| 文件頁數(shù)： | 15/76頁 |
| 文件大?。?/td> | 529K |
| 代理商： | ICS1531 |
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Chapter 3
Pin Diagram and Listings
ICS1531 Rev N 12/1/99
December, 1999
15
Copyright 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
3.2.3.4
Phase-Locked Loop Pins
Table 3-6
lists the pins for the phase-locked loop circuitry. For a block diagram that shows the function of
these pins, see
Figure 4-1
.
3.2.3.5
Industry-Standard 2-Wire Serial Bus Pins
Table 3-6.
Phase-Locked Loop Pins
Pin
Name
Pin
Type
Pin Description
EXTFIL
Input
External Filter.
This pin works with XFILRET (in this table, see XFILRET) and other components as part of an
optional external filter for the pixel phase-locked loop.
HSYNC
Input
Horizontal Sync.
This 5-V tolerant pin is the clock input for the pixel PLL.
Typically this pin is connected to the HSYNC from a PC display controller.
In this data sheet, this HSYNC signal is also called ‘input HSYNC’.
LOCK
Output
In this table, see the ‘STATUS’ pin name.
PDEN
Input
Phase-Detector Enable.
This pin is the input for the Phase/Frequency Detector enable that can suspend the charge
pump activity. It is 5-V tolerant. (For more information, see Reg 00:1-0 in
Section 6.5.1,
“Register 00h: Input Control Register”
.)
STATUS
Output
Status (Formerly called ‘Lock’).
This active-low pin works with Reg 2C:1-0 and Reg 12:3-2. The signal on this pin is:
Low when a lock condition occurs for one of the PLLs selected by Reg 2C:1-0 or 12:3-2.
High when no lock condition occurs for one of the PLLs selected by Reg 2C:1-0 or 12:3-2.
XFILRET
Input
External Filter Return.
This pin works with EXTFIL (in this table, see EXTFIL) and other components as part of an
optional external filter for the pixel phase-locked loop.
Table 3-7.
Industry-Standard 2-Wire Serial Bus Pins
Pin
Name
Pin
Type
Pin Description
SBADR
Input
Serial Bus Address.
This pin determines the address for the ICS1531 industry-standard 2-wire serial bus.
When the signal on this pin is:
– Low, the pixel bit address is 49h for read operations and 48h for write operations.
– High, the pixel bit address is 4Bh for read operations and 4Ah for write operations.
For more information on this pin, see
Section 2.9, “Industry-Standard 2-Wire Serial
Interface”
.
SCL
Input
Serial Clock.
This 5-V tolerant pin is the clock for the interface to an industry-standard 2-wire serial bus.
SDA
Input/
Output
Serial Data.
This 5-V tolerant pin connects to the data pin for an industry-standard 2-wire serial bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1560M-001 | Video/Graphics Clock Generator |
| ICS1560M-003 | Video/Graphics Clock Generator |
| ICS1560N-001 | Video/Graphics Clock Generator |
| ICS1560N-003 | Video/Graphics Clock Generator |
| ICS1561AM-706 | Video/Graphics Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1532 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR |
| ICS1560M-001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1560M-003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1560N-001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1560N-003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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