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| 型號(hào)： | ICS1531 |
| 英文描述： | Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator |
| 中文描述： | 三8位MSPS的的A / D轉(zhuǎn)換器與電源同步時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 44/76頁(yè) |
| 文件大?。?/td> | 529K |
| 代理商： | ICS1531 |
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ICS1531 Rev N 12/1/99
December, 1999
44
Chapter 6
Register Set
ICS1531 Data Sheet - Preliminary
Copyright 1999, Integrated Circuit Systems, Inc.
All rights reserved.
6.5.27
Register 2Ah: MCLK-SSOE
The MCLK-SSOE (MCLK Spread Spectrum Output Enable) Register is used to control the gain of the
MCLK PFD and spread spectrum. (To select values, see
Section 7.3, “Programming Spread Spectrum”
.)
6.5.28
Register 2Bh: MCLK-OE
The MCLK-OE (MCLK Output Enable) Register is used to enable the MCLK output and spread-spectrum
functionality. (To select values, see
Section 7.3, “Programming Spread Spectrum”
.)
Table 6-27.
MCLK-SSOE Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
2A:7-
2A:6
MCLK_SS [1-0]
MCLK Spread-Spectrum (Gain Select) [1-0].
0 = The gain is 1.
1 = The gain is 2.
2 = The gain is 4.
3 = The gain is 8.
R/W
D-MK
0
2A:5
Reserved
Reserved.
See
Section 6.1, “Reserved Bits”
.
This bit can be programmed to ‘0’.
–
–
0
2A:4-
2A:2
MCLK_PFD [2-0]
MCLK Phase/Frequency Detector (Gain Select) [2-0].
These bits determine the gain for the MCLK
Phase/Frequency Detector.
0 = The gain is 1.
1 = The gain is 2.
2 = The gain is 4.
3 = The gain is 8.
4 = The gain is 16, and so forth.
R/W
D-MK
0
2A:1-
2A:0
MCLK_OSD
[1-0]
MCLK Output Scaler Divider [1-0].
These bits determine the value for dividing the MCLK output
scaler.
0 = Division is by 1.
1 = Division is by 2.
2 = Division is by 4.
3 = Division is by 8.
R/W
D-MK
0
Table 6-28.
MCLK-OE Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
2B:7-
2B:2
Reserved
Reserved.
See
Section 6.1, “Reserved Bits”
.
These bits can be programmed to ‘0’.
–
–
0
2B:1
MCLK_SSENB
MCLK Spread-Spectrum Enable.
0 = Disable MCLK spread-spectrum functionality.
1 = Enable MCLK spread-spectrum functionality.
R/W
–
0
2B:0
MCLK_OE
MCLK Output Enable.
0 = Disable MCLK output.
1 = Enable MCLK output.
R/W
–
0
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