參數(shù)資料
型號(hào)： ICS1531
英文描述： Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
中文描述： 三8位MSPS的的A / D轉(zhuǎn)換器與電源同步時(shí)鐘發(fā)生器
文件頁(yè)數(shù)： 28/76頁(yè)
文件大?。?/td> 529K
代理商： ICS1531
ICS1531 Rev N 12/1/99
December, 1999
28
Chapter 6
Register Set
ICS1531 Data Sheet - Preliminary
Copyright 1999, Integrated Circuit Systems, Inc.
All rights reserved.
6.5
Register Definitions
The tables in this section specify for each register bit the reset value, if one exists. After a reset, the
ICS1531 sets all register bits to their default values.
Note:
1.
2.
3.
For the reserved bits, see
Section 6.1, “Reserved Bits”
.
For Register Set conventions, see
Section 6.2, “Register Set Conventions”
.
For acronyms used in this table, see
Section 6.3, “Register Set Abbreviations and Acronyms”
.
6.5.1
Register 00h: Input Control Register
The Input Control Register is used to select inputs that control the pixel PLL Phase/Frequency Detector.
Table 6-3.
Input Control Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
00:7-
00:6
HSYNC_Sel [1-0]
Horizontal Sync Select [1-0].
These multiplexed bits select one of possible four Schmitt
triggers that connect to the input HSYNC pin.
0 = Schmitt trigger 0
1 = Schmitt trigger 1
2 = Schmitt trigger 2. (Recommended setting.)
3 = Schmitt trigger 3
–
–
0
00:5
In_Sel
Input Select.
This bit selects an input to the Phase/Frequency Detector.
0 = The input is HSYNC.
1 = The input is OSC (default).
–
–
1
00:4
Fdbk Div Load
Feedback Divider Load Control.
This bit selects a load for the internal feedback divider.
0 = The load is on the pixel PLL reset.
1 = The load is on the next scan line.
R/W
–
0
00:3
Fdbk_Pol
Feedback Polarity.
This bit selects the polarity of the feedback signal to the
Phase/ Frequency Detector.
0 = The polarity is positive edge.
1 = The polarity is negative edge.
R/W
–
0
00:2
Ref_Pol
(External) Reference Polarity.
This bit selects the polarity of REF, the reference signal
provided by the input HSYNC to the Phase/Frequency
Detector.
0 = The polarity is positive edge.
1 = The polarity is negative edge.
R/W
–
0
00:1
PD_Pol
Phase/(Frequency) Detector Polarity.
This bit selects the polarity of the PDEN signal to the
Phase/Frequency Detector.
0 = The signal from the PDEN pin is active high.
1 = The signal from the PDEN pin is active low.
Note:
This bit is disabled when Reg 00:0 = 1.
R/W
–
0
相關(guān)PDF資料
PDF描述
ICS1560M-001 Video/Graphics Clock Generator
ICS1560M-003 Video/Graphics Clock Generator
ICS1560N-001 Video/Graphics Clock Generator
ICS1560N-003 Video/Graphics Clock Generator
ICS1561AM-706 Video/Graphics Clock Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1532 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
ICS1560M-001 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
ICS1560M-003 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
ICS1560N-001 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
ICS1560N-003 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
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