參數(shù)資料
型號(hào)： ICS1531
英文描述： Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
中文描述： 三8位MSPS的的A / D轉(zhuǎn)換器與電源同步時(shí)鐘發(fā)生器
文件頁(yè)數(shù)： 33/76頁(yè)
文件大小： 529K
代理商： ICS1531
Chapter 6
Register Set
ICS1531 Rev N 12/1/99
December, 1999
33
Copyright 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
6.5.7
Register 06h: Output Enables
The Output Enables Register is used to select and enable various outputs.
Note:
Table 6-10
refers to ADC_FUNC, an internally generated signal that is delayed so it is in the same
domain as the internal ADC_CLK signal (that is, the pixel clock). Functionally, depending on the
setting of Reg 06:3, ADC_FUNC is equivalent to either ADCSYNC (which provides recovered
HSYNC) or the input HSYNC.
Table 6-10.
Output Enables Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
06:7
Reserved
Reserved.
See
Section 6.1, “Reserved Bits”
.
This bit can be programmed to ‘0’.
–
–
0
06:6
OE_Tck
Output Enable Clock.
This bit enables the pixel clock output on the CLK pin.
0 = The pixel clock output is disabled (high- impedance).
1 = The pixel clock output is enabled.
–
–
0
06:5
OE_ADCRCLK
Output Enable for ADCRCLK.
This bit enables the clock output for ADCRCLK. When this bit is:
0 = The following are both true:
– The clock output for the ADC is disabled (that is, high-
impedance).
– Because the clock source for the ADC is accepted from
the ADCRCLK pin, an external clock can be provided to
the ADC.
1 = The following are both true:
– The clock output for the ADC is enabled.
– The input multiplexer selects the internal pixel clock.
–
–
0
06:4
OE_ADCSYNC
Output Enable for ADCSYNC.
This bit enables the output for ADCSYNC. When this bit is:
0 = The following are both true:
– The output for the ADCSYNC signal is disabled (high-
impedance).
– An external sync signal for the ADC is accepted from the
ADCSYNC pin.
1 = The following are both true:
– The output for the ADCSYNC signal is enabled.
– The input multiplexer selects the internal sync signal.
R/W
–
0
06:3
FUNC_Sel
FUNC Select.
This bit selects the source of the signal to ADC_FUNC. (See the
note at the first of this table.)
0 = The source is recovered HSYNC.
1 = The source is REF, the input HYSNC signal that is
conditioned before it goes to the phase-locked loop block.
–
–
0
相關(guān)PDF資料
PDF描述
ICS1560M-001 Video/Graphics Clock Generator
ICS1560M-003 Video/Graphics Clock Generator
ICS1560N-001 Video/Graphics Clock Generator
ICS1560N-003 Video/Graphics Clock Generator
ICS1561AM-706 Video/Graphics Clock Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1532 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
ICS1560M-001 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
ICS1560M-003 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
ICS1560N-001 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
ICS1560N-003 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator
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