參數(shù)資料
型號(hào)： HY27US08121B-FIB
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： PROM
英文描述： 64M X 8 FLASH 3.3V PROM, 18 ns, PBGA63
封裝： 9 X 11 MM, 1 MM HEIGHT, 0.80 MM PITCH, FBGA-63
文件頁(yè)數(shù)： 4/40頁(yè)
文件大小： 360K
代理商： HY27US08121B-FIB
Rev 0.5 / Jul. 2007
12
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Three types of operations are available: random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 words (x16
device) of data within the selected page are transferred to the data registers in less than access random read time tR
(12us). The system controller can detect the completion of this data transfer tR (12us) by analyzing the output of R/B
pin. Once the data in a page is loaded into the registers, they may be read out in 30ns cycle time by sequentially puls-
ing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last
column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE
high.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Writing
the Read2 command user may selectively access the spare area of bytes 512 to 527 (x8 device) or words 256 to 263
(x16 device). Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored.
Unless the operation is aborted, the page address is automatically incremented for sequential row
Read as in Read1 operation and spare sixteen bytes of each page (x8 device) or eight words of each page (x16 device)
may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area.
The Read2 command (50h) is needed to move the pointer back to the spare area.
Figure_11 to 14 show typical sequence and timings for each read operation.
3.2 Page Program.
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or
consecutive bytes up to 528 (x8 device), in a single page program cycle. The number of consecutive partial page pro-
gramming operations within the same page without an intervening erase operation must not exceed 1 for main array
and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a
serial data loading period in which up to 528 bytes (x8 device) or 264 word (x16 device) of data may be loaded into
the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation,
please refer to Figure 24 The data-loading sequence begins by inputting the Serial Data Input command (80h), fol-
lowed by the four address input cycles and then serial data loading. The Page Program confirm command (10h) starts
the programming process. Writing 10h alone without previously entering the serial data will not initiate the program-
ming process. The internal Program Erase Controller automatically executes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered, with RE and CE low, to read the status register. The system controller can
detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register.
Only the Read Status command and Reset command are valid while programming is in progress. When the Page Pro-
gram is complete, the Write Status Bit (I/O 0) may be checked in Figure 15 The internal write verify detects only errors
for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode
until another valid command is written to the command register.
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