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參數(shù)資料
| 型號： | HY27UA081G1M-TIB |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | PROM |
| 英文描述： | 128M X 8 FLASH 3.3V PROM, 12000 ns, PDSO48 |
| 封裝： | 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48 |
| 文件頁數(shù)： | 1/43頁 |
| 文件大?。?/td> | 729K |
| 代理商： | HY27UA081G1M-TIB |
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This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Oct. 2004
1
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
No.
History
Draft Date
Remark
0.0
1) Initial Draft
Nov. 28. 2003
Preliminary
0.1
1) Add 1.8V Operation Product to Data sheet
Mar. 11. 2004
Preliminary
0.2
1) Change AC Characteristics
- tWP(25ns->40ns), tWC(50ns->60ns),
- tRP(30ns->40ns), tRC(50ns->60ns),
- tREADID(35ns->45ns)
Apr. 29. 2004
Preliminary
0.3
1) Add Errata (3V Product)
2) Add Applicaiton Note
Reset command must be issued when the controller writes data to
another 512Mb.(i.e. When A26 is changed during program.)
3) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page22)
4) Add the description of System Interface Using /CE don’t care (Page37)
May. 14. 2004
Preliminary
0.4
1) Delete Errata
2) Change Characteristics
3) Delete Cache Program
Jun. 01. 2004
Preliminary
0.5
1) Change TSOP1, WSOP1, FBGA package dimension
2) Edit TSOP1, WSOP1 package figures
3) Change FBGA package figure
Oct. 20. 2004
tWH
tREH
Specification
15
Relaxed value
20
tCRY
tREA@ID Read
Before
60 + tr
35
After
70 + tr
45
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