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參數(shù)資料
| 型號(hào)： | HIP8112A |
| 廠商： | Harris Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 719K |
| 代理商： | HIP8112A |
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4-21
TABLE 29. SOFTWARE RESET AND VIDEO STATUS REGISTER
SUB ADDRESS = 0x17
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7
Software Reset
When this bit is set to 1, the entire device except the I
2
C bus is reset to a known state
exactly like the RESET input. The software reset will initialize all register bits to their reset
state. Once set this bit is self clearing after only 4 CLK periods. This bit is cleared on pow-
er-up by the external RESET pin.
0
B
6
Black Screen
This flag when set (‘1’) will set the output video to black when a lost vertical sync has
been detect. This flag is cleared after a RESET.
0
B
5
Line LOCKED Flag
This flag when set (‘1’) indicates that the Line Locked-Phase Locked Loop has locked to
the video data. This flag is read only and cleared after a RESET or Software Reset.
0
B
4
Standard Error Flag
This flag when set (‘1’) indicates that the Standard detected does not match the one se-
lected in the Video Input Control Register. The standard is checked against a line count
and if the line count is significantly different than the expected value then this flag is trig-
gered. This flag is read only and cleared after a RESET or Software Reset.
0
B
3 - 0
Not Used
Write ignored, Read 0’s.
0000
B
TABLE 30. RESERVED
SUB ADDRESS = 0x18
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Reserved
This register is reserved. This register will read all zero’s and is write ignored.
0000 0000
B
TABLE 31. RESERVED
SUB ADDRESS = 0x19
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 6
Reserved
This register is reserved. This register will read all zero’s and is write ignored.
00
B
5
Lost HSYNC
Control (SNAP Bit)
This bit controls when the PLL will declare lost horizontal sync, leave track mode and re-
turn to acquisition to acquire a new HSYNC reference. When this bit is cleared, lost line
lock is declared after 12 missing horizontal syncs. When this bit is set, lost line lock is
declared after one missing horizontal sync. This bit is cleared by RESET.
0
B
4 - 0
Reserved
This register is reserved. This register will read all zero’s and is write ignored.
0 0000
B
TABLE 32. RESERVED
SUB ADDRESS = 0x1A
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Reserved
This register is reserved. This register will read all zero’s and is write ignored.
0000 0000
B
TABLE 33. PRODUCT ID REGISTER
SUB ADDRESS = 0x1B
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Product ID Code
This register contains the last two digits of the product part number for use as a software
ID. These bits are read only and always read 0x12.
0001 0010
B
(0x12)
HMP8112A
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