參數(shù)資料
型號(hào)： HIP8112A
廠商： Harris Corporation
英文描述： NTSC/PAL Video Decoder
中文描述： NTSC / PAL視頻解碼器
文件頁(yè)數(shù)： 20/40頁(yè)
文件大小： 719K
代理商： HIP8112A
4-20
TABLE 26. DC RESTORE END TIME (LSB) REGISTER
SUB ADDRESS = 0x14
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
DC RESTORE
END Time (LSB)
This register provides a programmable delay for the internal DC RESTORE signal. This
is the lower byte of the 10-bit word.
0101 0010
B
(0x52)
TABLE 27. DC RESTORE END TIME (MSB) REGISTER
SUB ADDRESS = 0x15
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
0000 0000
B
(0x00)
9 - 8
DC RESTORE
END Time (MSB)
This register provides a programmable delay for the internal DC RESTORE signal. This
is the upper byte of the 10-bit word.
TABLE 28. OUTPUT FORMAT CONTROL REGISTER
SUB ADDRESS = 0x16
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7
Square Pixel/ITU-R
BT601 Select
When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected.
0
B
6, 5, 4
Output Field Control
“FLD_CONT(2-0)”
These bits control the field capture rate of the HMP8112A. The user can select every 4th
field, every other field or every field of video to be output to the data port.
000 = No Capture Enabled
001 = Capture every 4th field
010 = Capture every 2nd field
011 = Capture every 2nd odd field
100 = Capture every 2nd even field
101 = Capture every odd field
110 = Capture every even field
111 = Capture all fields
000
B
3
8/16 output Select
When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchro-
nous Pixel Transfer output mode is selected.
0
B
2
OEN
This bit enables the Y(7-0), CbCr(7-0), ACTIVE, FIELD, HSYNC, VSYNC and DVLD out-
puts. 1 = Outputs enabled; 0 = three-stated.
0
B
1
Vertical Pixel Siting
When this bit is cleared (‘0’) the chrominance pixels have a 1/2 line pixel offset from their
associated luminance pixel in a 4:2:2 subsampled scheme. When this bit is set (‘1’) the
pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. The
bit is cleared by a RESET.
0
B
0
Not Used
Write Ignored, Read 0’s
0
B
HMP8112A
相關(guān)PDF資料
PDF描述
HIR19-21C Technical Data Sheet 0.8mm Height Flat Top Infrared LED
HIR19-L11 Technical Data Sheet 0.8mm Height Flat Top Infrared LED
HIR204C 3mm Infrared LED, T-1
HIR 5mm Infrared LED, T-1 3/4
HIR333 5mm Infrared LED, T-1 3/4
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP-8V 制造商:Belden Inc 功能描述:SPLITTER 8 WAY
HIP9010 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Engine Knock Signal Processor
HIP9010AB 制造商:Intersil Corporation 功能描述:
HIP9011 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Engine Knock Signal Processor
HIP9011_06 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Engine Knock Signal Processor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*