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參數(shù)資料
| 型號： | HIP8112A |
| 廠商： | Harris Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 719K |
| 代理商： | HIP8112A |
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4-19
TABLE 20. HSYNC END TIME (LSB) REGISTER
SUB ADDRESS = 0x0E
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
HSYNC Pulse
END Time (LSB)
This register provides a programmable delay for the external HSYNC pulse. This is the
lower byte of the 10-bit word.
0010 0000
B
(0x20)
TABLE 21. HSYNC END TIME (MSB) REGISTER
SUB ADDRESS = 0x0F
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
0000 0000
B
(0x00)
9 - 8
HSYNC Pulse
END Time (MSB)
This register provides a programmable delay for the external HSYNC pulse. This is the
upper byte of the 10-bit word.
TABLE 22. PLL FILTER ADJUST REGISTER
SUB ADDRESS = 0x10
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
PLL Filter Adjust
Register
The Phase Locked Loop (PLL) time constants can be changed for testing purposes. It is
recommended that the default value of 0x20 always be used. The reset state is 0x00.
0000 0000
B
(0x00)
TABLE 23. PLL SYNC DETECT WINDOW REGISTER
SUB ADDRESS = 0x11
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
PLL Horizontal Sync
Detect Window
These bits control the PLL horizontal sync detect window. This window sets the length
of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of
this window are declared missing and will cause the missing sync logic to start counting
missing syncs.
1101 1101
B
(0xDD)
TABLE 24. DC RESTORE START TIME (LSB) REGISTER
SUB ADDRESS = 0x12
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
DC RESTORE
START Time (LSB)
This register provides a programmable delay for the internal DC RESTORE signal. This
is the lower byte of the 10-bit word.
0011 0111
B
(0x3F)
TABLE 25. DC RESTORE START TIME (MSB) REGISTER
SUB ADDRESS = 0x13
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
0000 0000
B
(0x00)
9 - 8
DC RESTORE
START Time (MSB)
This register provides a programmable delay for the internal DC RESTORE signal. This
is the upper byte of the 10-bit word.
HMP8112A
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