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參數(shù)資料
| 型號： | HIP8112A |
| 廠商： | Harris Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 12/40頁 |
| 文件大?。?/td> | 719K |
| 代理商： | HIP8112A |
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4-12
NOTES:
1. Y
0
is the first active luminance pixel of a line. Cb
0
and Cr
0
are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
due to the 4:2:2 subsampling. Y
N
the last valid pixel in the blanking period.
2. ACTIVE is asserted per Figure 13.
3. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD is not a 50% duty cycle synchronous output and will
appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 14. OUTPUT TIMING 16-BIT MODE
Y
0
Y
N
Cb
0
Cr
N
Y
1
Cr
0
Y
2
Cb
2
Y
3
Cr
2
Y
4
Cb
4
CLK
DVLD
ACTIVE
Y[7-0]
CbCr[7-0]
t
DVLD
NOTE 1
NOTE 2
NOTE 3
CLK
DVLD
ACTIVE
Y[7-0]
t
DVLD
Cb
0
Y
0
Cr
0
Cb
2
Y
2
Cr
2
Y
1
Y
3
Cb
4
NOTES:
4. Y
0
is the first active luminance pixel of a line. Cb
0
and Cr
0
are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
due to the 4:2:2 subsampling. Pixel data is not output during the blanking period.
5. ACTIVE stays asserted as soon as 8-Bit mode is selected.
6. DVLD is asserted for every valid pixel during the active region only per Figure 13. DVLD may deassert briefly during the active video region
as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 15. OUTPUT TIMING 8-BIT MODE
NOTE 6
NOTE 4
NOTE 5
HMP8112A
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