參數(shù)資料
型號: HB52E169E12
廠商: Hitachi,Ltd.
英文描述: 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM)
中文描述: 128 MB的注冊SDRAM的內存(128 MB的寄存同步的DRAM內存)
文件頁數(shù): 4/53頁
文件大?。?/td> 1737K
代理商: HB52E169E12
HB52E169E12-F
4
Note: 1.
REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
Serial PD Matrix*
1
SA0 to SA2
V
CC
V
SS
NC
Serial address input
Primary positive power supply
Ground
No connection
Byte
No.
0
Function described
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses
bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest CE latency)
10 ns
SDRAM access from Clock
(highest CE latency)
6 ns
Module configuration type
Refresh rate/type
Bit
7
1
Bit
6
0
Bit
5
0
Bit
4
0
Bit
3
0
Bit
2
0
Bit
1
0
Bit
0
0
Hex value Comments
80
128
1
2
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
0
0
1
0
0
0
0
08
04
0C
0A
256 byte
SDRAM
12
10
5
6
7
8
9
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
01
48
00
01
A0
1
72 bit
0 (+)
LVTTL
CL = 3
10
0
1
1
0
0
0
0
0
60
*
7
11
12
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
02
80
ECC
Normal
(15.625
μ
s)
Self refresh
16M
×
4
×
4
1 CLK
13
14
15
SDRAM width
Error checking SDRAM width
SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE latency
(-A6F)
(-B6F)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
04
04
01
16
1
0
0
0
1
1
1
1
8F
1, 2, 4, 8,
full page
4
17
0
0
0
0
0
1
0
0
04
18
0
0
0
0
0
1
1
0
06
2, 3
0
0
0
0
0
1
0
0
04
3
Pin name
Function
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