參數(shù)資料
型號： HB52E169E12
廠商： Hitachi,Ltd.
英文描述： 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM)
中文描述： 128 MB的注冊SDRAM的內(nèi)存（128 MB的寄存同步的DRAM內(nèi)存）
文件頁數(shù)： 15/53頁
文件大?。?/td> 1737K
代理商： HB52E169E12
HB52E169E12-F
15
Notes: 1. I
RCD
to I
RRD
are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
Pin Functions
CK0 to CK3 (input pin):
CK is the master clock input to this pin. The other input signals are referred at
CK rising edge.
S0, S2 (input pin):
When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins):
Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the com-
bination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins):
Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to level at the read or
write command cycle CK rising edge. And this column address becomes burst access start address. A10 de-
fines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But
when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BA) is pre-
charged.
A12/A13 (input pin):
A12/A13 are bank select signal (BA). The memory array is divided into bank 0, bank
1, bank 2 and bank 3. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low,
bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank
3 is selected.
CKE0 (input pin):
This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and
clock suspend modes.
DQMB0 to DQMB7 (input pins):
Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins):
Data is input to and output from these pins.
S to command disable
Power down exit to command input
Burst stop to output valid data hold
(CE latency = 3)
(CE latency = 4)
Burst stop to output high impedance
(CE latency = 3)
(CE latency = 4)
Burst stop to write data ignore
I
CDD
I
PEC
0
1
I
BSR
I
BSR
2
3
I
BSH
I
BSH
I
BSW
3
4
1
Parameter
Frequency (MHz)
t
CK
(ns)
HITACHI
Symbol
PC100
Symbol
HB52E169E12
-A6F/B6F
100
10
Notes
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