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| 型號(hào)： | DV164136 |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 80/107頁(yè) |
| 文件大小： | 0K |
| 描述： | DEVELOPMENT KIT FOR PIC18 |
| 產(chǎn)品培訓(xùn)模塊： | PIC18 J Series MCU Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PIC® |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | PIC18F8722，PIC18F87J11 |
| 所含物品： | 板，線纜，CD，PICkit? 3 個(gè)編程器，電源 |
| 產(chǎn)品目錄頁(yè)面： | 659 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | PIC18F87J11-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F87J11T-I/PTTR-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722T-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722T-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP |
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PIC18F87J11 FAMILY
DS39778E-page 74
2007-2012 Microchip Technology Inc.
6.2
PIC18 Instruction Cycle
6.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping, quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the Program Counter
is incremented on every Q1. The instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
6.2.2
INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the Program Counter to change
(e.g., GOTO), then two cycles are required to complete
the instruction (Example 6-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 6-5:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC
PC + 2
PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. BRA SUB_1
Fetch 3
Execute 3
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
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