參數(shù)資料
型號(hào)： DV164136
廠商： Microchip Technology
文件頁(yè)數(shù)： 6/107頁(yè)
文件大?。?/td> 0K
描述： DEVELOPMENT KIT FOR PIC18
產(chǎn)品培訓(xùn)模塊： PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝： 1
系列： PIC®
類型： MCU
適用于相關(guān)產(chǎn)品： PIC18F8722，PIC18F87J11
所含物品： 板，線纜，CD，PICkit? 3 個(gè)編程器，電源
產(chǎn)品目錄頁(yè)面： 659 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： PIC18F87J11-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F87J11T-I/PTTR-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
2007-2012 Microchip Technology Inc.
DS39778E-page 103
PIC18F87J11 FAMILY
7.5.2
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD
PROGRAMMING).
The PIC18F87J11 family of devices have a feature that
allows programming a single word (two bytes). This
feature is enable when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
1.
Load the Table Pointer register with the address
of the data to be written
2.
Write the 2 bytes into the holding registers and
perform a table write
3.
Set the WREN bit (EECON1<2>) to enable byte
writes.
4.
Disable interrupts.
5.
Write H'55' to EECON2.
6.
Write H'AA' to EECON2.
7.
Set the WR bit. This will begin the write cycle.
8.
The CPU will stall for duration of the write for TIW
(see Parameter D133A).
9.
Re-enable interrupts.
EXAMPLE 7-4:
SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY
MOVLW
CODE_ADDR_UPPER
; Load TBLPTR with the base address
MOVWF
TBLPTRU
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
MOVLW
DATA0
MOVWF
TABLAT
TBLWT*+
MOVLW
DATA1
MOVWF
TABLAT
TBLWT*
PROGRAM_MEMORY
BSF
EECON1, WPROG
; enable single word write
BSF
EECON1, WREN
; enable write to memory
BCF
INTCON, GIE
; disable interrupts
MOVLW
H'55'
Required
MOVWF
EECON2
; write H'55'
Sequence
MOVLW
H'AA'
MOVWF
EECON2
; write H'AA'
BSF
EECON1, WR
; start program (CPU stall)
BSF
INTCON, GIE
; re-enable interrupts
BCF
EECON1, WPROG
; disable single word write
BCF
EECON1, WREN
; disable write to memory
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