參數(shù)資料
型號(hào)： DV164136
廠商： Microchip Technology
文件頁(yè)數(shù)： 40/107頁(yè)
文件大?。?/td> 0K
描述： DEVELOPMENT KIT FOR PIC18
產(chǎn)品培訓(xùn)模塊： PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝： 1
系列： PIC®
類型： MCU
適用于相關(guān)產(chǎn)品： PIC18F8722，PIC18F87J11
所含物品： 板，線纜，CD，PICkit? 3 個(gè)編程器，電源
產(chǎn)品目錄頁(yè)面： 659 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： PIC18F87J11-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F87J11T-I/PTTR-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F87J11 FAMILY
DS39778E-page 38
2007-2012 Microchip Technology Inc.
3.2
Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) (see
).
REGISTER 3-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1)
R/W-0
R/W-1
R/W-0
R(2)
U-1
R/W-0
IDLEN
IRCF2(3)
IRCF1(3)
IRCF0(3)
OSTS
—SCS1(5)
SCS0(5)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN:
Idle Enable bit
1
= Device enters an Idle mode when a SLEEP instruction is executed
0
= Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4
IRCF<2:0>:
INTOSC Source Frequency Select bits(3)
111
= 8 MHz (INTOSC drives clock directly)
110
= 4 MHz (default)
101
= 2 MHz
100
= 1 MHz
011
= 500 kHz
010
= 250 kHz
001
= 125 kHz
000
= 31 kHz (from either INTOSC/256 or INTRC)(4)
bit 3
OSTS:
Oscillator Start-up Timer Time-out Status bit(2)
1
= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0
= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
Unimplemented:
Read as ‘1’
bit 1-0
SCS<1:0>:
System Clock Select bits(5)
11
= Internal oscillator block
10
= Primary oscillator
01
= Timer1 oscillator
00
= Default primary oscillator (as defined by the FOSC<2:0> Configuration bits)
Note 1:
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2:
Reset state depends on the state of the IESO Configuration bit.
3:
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
4:
The source is selected by the INTSRC bit (OSCTUNE<7>), see text.
5:
Modifying these bits will cause an immediate clock source switch.
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