參數(shù)資料
型號： DV164136
廠商： Microchip Technology
文件頁數(shù)： 3/107頁
文件大小： 0K
描述： DEVELOPMENT KIT FOR PIC18
產(chǎn)品培訓模塊： PIC18 J Series MCU Overview
標準包裝： 1
系列： PIC®
類型： MCU
適用于相關產(chǎn)品： PIC18F8722，PIC18F87J11
所含物品： 板，線纜，CD，PICkit? 3 個編程器，電源
產(chǎn)品目錄頁面： 659 (CN2011-ZH PDF)
相關產(chǎn)品： PIC18F87J11-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F87J11T-I/PTTR-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
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PIC18F87J11 FAMILY
DS39778E-page 100
2007-2012 Microchip Technology Inc.
7.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
Load Table Pointer register with address of row
being erased.
2.
Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3.
Disable interrupts.
4.
Write H'55' to EECON2.
5.
Write H'AA' to EECON2.
6.
Set the WR bit. This will begin the row erase
cycle.
7.
The CPU will stall for duration of the erase for
TIW (see Parameter D133A).
8.
Re-enable interrupts.
EXAMPLE 7-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
CODE_ADDR_UPPER
; load TBLPTR with the base
MOVWF
TBLPTRU
; address of the memory block
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
ERASE_ROW
BSF
EECON1, WREN
; enable write to memory
BSF
EECON1, FREE
; enable Row Erase operation
BCF
INTCON, GIE
; disable interrupts
Required
MOVLW
H'55'
Sequence
MOVWF
EECON2
; write H'55'
MOVLW
H'AA'
MOVWF
EECON2
; write H'AA'
BSF
EECON1, WR
; start erase (CPU stall)
BSF
INTCON, GIE
; re-enable interrupts
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