參數(shù)資料
型號： DV164136
廠商： Microchip Technology
文件頁數(shù)： 54/107頁
文件大?。?/td> 0K
描述： DEVELOPMENT KIT FOR PIC18
產(chǎn)品培訓(xùn)模塊： PIC18 J Series MCU Overview
標準包裝： 1
系列： PIC®
類型： MCU
適用于相關(guān)產(chǎn)品： PIC18F8722，PIC18F87J11
所含物品： 板，線纜，CD，PICkit? 3 個編程器，電源
產(chǎn)品目錄頁面： 659 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： PIC18F87J11-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F87J11T-I/PTTR-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722T-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F8722-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP
PIC18F87J11 FAMILY
DS39778E-page 50
2007-2012 Microchip Technology Inc.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS<1:0> to ‘11’.
When the clock source is switched to the internal
oscillator block (see Figure 4-3), the primary oscillator
is shut down and the OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the pri-
mary clock occurs (see Figure 4-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCSx bits are not affected by the switch. The INTRC
block source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
123
n-1
n
Clock Transition
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTRC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q3
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> Bits Changed
TPLL(1)
12
n-1 n
Clock
OSTS Bit Set
Transition
TOST(1)
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