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Lucent Technologies Inc.
57
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
5 Software Architecture (continued)
5.2
Register Settings (continued)
Table 47. pllc Register Fields
Bit
15—14
13—11
10—9
8—6
5—0
Field
LF
ICP
N
K
M
Bit
Field
Description
15—14
LF[1:0]
PLL Loop Filter Control. TBD settings based on desired VCO frequency*.
*
Keep N = 0 when possible, VCO range: 50 MHz—150 MHz.
13—11
ICP[2:0]
PLL Charge Pump Control.
10—9
N[1:0]
PLL Input Clock Divider. 2-bit positive integer from 0 to 3.
8—6
K[2:0]
PLL Output Divider. 3-bit positive integer from 0 to 7.
5—0
M[5:0]
PLL Multiplier. 6-bit positive integer from 0 to 63.
Table 48. psw (Processor Status Word) Register
Bit
15—12
11—10
9
8—5
4
3—0
Field
DAU Flags
Res
a1[V]
a1[35:32]
a0[V]
a0[35:32]
Bit
Field
Value
Description
15—12
DAU Flags*
* The DAU flags are set by multiply/ALU (F1), conditionals (F2), ALU (F3), or BMU (F4) operations involving the
accumulators.
WXXX
LMI—logical minus when set (bit 35 = 1).
XWXX
LEQ—logical equal when set (bit 35:0 = 0).
XXWX
LLV—logical overflow when set.
XXXW
LMV—mathematical overflow when set.
11—10
Res
—
Reserved—read as zero, write as zero.
9
a1[V]
W
Accumulator 1 (a1) overflow when set.
8—5
a1[35:32]
WXXX
Accumulator 1 (a1) bit 35.
XWXX
Accumulator 1 (a1) bit 34.
XXWX
Accumulator 1 (a1) bit 33.
XXXW
Accumulator 1 (a1) bit 32.
4
a0[V]
W
Accumulator 0 (a0) overflow when set.
3—0
a0[35:32]
WXXX
Accumulator 0 (a0) bit 35.
XWXX
Accumulator 0 (a0) bit 34.
XXWX
Accumulator 0 (a0) bit 33.
XXXW
Accumulator 0 (a0) bit 32.
VCO FREQUENCY
()
CLKIN M
2
+
()
N1
+
()
---------------------------------------
=
MIPS rate
CLKIN M
2
+
()
2N
1
+
()
K1
+
()
()
----------------------------------------------------
=