參數(shù)資料
型號: B900M24FXX12IT
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件頁數(shù): 15/100頁
文件大小: 1547K
代理商: B900M24FXX12IT
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Lucent Technologies Inc.
21
4 Hardware Architecture (continued)
4.2
DSP1600 Core Architectural Overview (continued)
Table 10. DSP1600 Core Block Diagram Legend
Symbol
Name
16 x 16 MPY
16-bit by 16-bit multiplier
a0—a1
Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l)*
* F3 ALU instructions with immediates require specifying the high half of the accumulators as a0h and a1h.
alf
Low-power standby mode and memory map control
ALU/SHIFT
Arithmetic logic unit/shifter
auc
Arithmetic unit control
c0—c2
Counters 0—2
cloop
Cache loop count
CMP
Comparator
DAU
Digital arithmetic unit
i
Increment register
IDB
Internal data bus
inc
Interrupt control
ins
Interrupt status
j
Increment register
k
Increment register
MUX
Multiplexer
p
Product register (16-bit halves specified as p, pl)
PC
Program counter
pi
Program interrupt return register
pr
Program return register
psw
Processor status word
pt
X address space pointer
r0—r3
Y address space pointers
rb
Modulo addressing register (begin address)
re
Modulo addressing register (end address)
SYS
System cache and control section
x
Multiplier input register
XAAU
X space address arithmetic unit
XAB
X space address bus
XDB
X space data bus
YAAU
Y space address arithmetic unit
YAB
Y space address bus
YDB
Y space data bus
ybase
Direct addressing base register
y
DAU register (16-bit halves specified as y, yl)
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