參數(shù)資料
型號： B900M24FXX12IT
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件頁數(shù)： 12/100頁
文件大?。?/td> 1547K
代理商： B900M24FXX12IT
Lucent Technologies Inc.
19
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
4 Hardware Architecture (continued)
4.1
B900 Architectural Overview (continued)
4.1.8 Synchronous Serial Interface Units (SSI)
One independent SSI unit is compatible with the SPI
interface of the
Motorola* 68HC11 microcontroller. All
the features of the 68HC11 SPI interface are supported
except the open collector mode of operation and slave-
initiated transfers, which are not supported. The B900
core can be interrupted upon completion of an SSI
data transfer. The SSI pins are multiplexed with IOPC,
under control of a programmable bit in the SSI. For
more information, see Section 4.6.
4.1.9 Clock Generation
The clock structure for the B900 incorporates a wide
range of options, including a crystal oscillator, a PLL, a
low-frequency divider, and an internal ring oscillator.
The B900 core receives a 2X B900 core clock (two
times MIPS rate) that is divided by two inside the core
to generate the DSP’s non-wait-stated and wait-stated
clocks.
It includes one low-power internal ring oscillator and a
crystal oscillator that connects to an external crystal.
The clkc register bits 7—3 (see Table 41 on page 53)
determine which clock is selected to run the core and
peripherals.
The B900 provides an output clock pin, DOUT. As
shown in Table 9, clkc register bits 8—11 select one of
the DOUT MUX pin output functions.
* Motorola is a registered trademark of Motorola, Inc.
4.1.10 Dual-Channel Serial I/O Port (SIO)
The SIO provides a serial interface to codecs or other
external devices.
See Section 4.10 for more information.
4.1.11 Bit Manipulation Unit (BMU)
The BMU extends the DSP1600 core instruction set to
provide more efficient bit operations on accumulators.
The BMU contains logic for barrel shifting, normaliza-
tion, and bit-field insertion/extraction. The unit also
contains a set of 36-bit alternate accumulators. The
data in the alternate accumulators can be shuffled with
the data in the main accumulators. Flags returned by
the BMU mesh seamlessly with the DSP1600 condi-
tional instructions.
Table 9. DOUT Pin Output Functions
clkc
Register
DOUT MUX[3:0] Pin Output Function
Bits 11—8
0000
Ring oscillator (CLKRING) selected to
DOUT
0001
Input crystal/clock (CLKIN) selected to
DOUT
0010
Low-frequency clock (CLKLOW)
selected to DOUT
0011
Wait-stated B900 (CLKWAIT) clock
selected to DOUT
0100
Free-running B900 (CLKFREE) clock
selected to DOUT
0101
Reserved
0110
Logic 0 selected to DOUT
0111
Logic 1 selected to DOUT
1xxx
Reserved
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